We present a compiler technique, which is based on Shasha and Snir's delay set analysis, to hide the underlying relaxed memory consistency model for an optimizing compiler for explicitly parallel programs. The compiler presents programmers with a sequentially consistent view of the underlying machine irrespective of whether it follows a sequentially consistent model or a relaxed model. To hide the underlying relaxed memory consistency model and to guarantee sequential consistency, our algorithm inserts fence instructions by identifying memory-barrier nodes. We reduce the number of fence instructions by exploiting the ordering constraints of the underlying memory consistency model and the property of fence and synchronization operations. We introduce dominators with respect to a node in a control flow graph to identify memory-barrier nodes. We also show that minimizing the number of memory-barrier nodes by using dominators with respect to a node is NP-hard.
|Original language||English (US)|
|Number of pages||12|
|Journal||Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT|
|State||Published - Jan 1 2000|
ASJC Scopus subject areas
- Theoretical Computer Science
- Hardware and Architecture