TY - GEN
T1 - Heterogeneous integration of light-emitting transistors on silicon for hybrid electronic-photonic logic circuitry
AU - Carlson, John A.
AU - Dallesasse, John M.
N1 - An array of three-terminal LETs is designed and fabricated into heterogeneously integrated epitaxial material for the purposes of establishing hybrid electronic-photonic circuitry. Monolithically-integrated LETs are characterized to compare the performance of integrated devices in verifying the integration process, as well as the device structure of the integrated LET is analyzed for performance optimization. This work is sponsored in part by E2CDA-NRI, a funded center of NRI, a Semiconductor Research Corporation (SRC) program sponsored by NERC and NIST, and in part by the National Science Foundation (NSF) under Grant No. ECCS 16-40196.
PY - 2019
Y1 - 2019
N2 - An array of heterogeneously integrated light-emitting transistors is fabricated after an epitaxial transfer process bonds and interconnects active III-V photonic material onto a CMOS-compatible host wafer for the purposes of establishing a photonic logic network.
AB - An array of heterogeneously integrated light-emitting transistors is fabricated after an epitaxial transfer process bonds and interconnects active III-V photonic material onto a CMOS-compatible host wafer for the purposes of establishing a photonic logic network.
UR - http://www.scopus.com/inward/record.url?scp=85068152096&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85068152096&partnerID=8YFLogxK
U2 - 10.1364/CLEO_AT.2019.JTh2A.60
DO - 10.1364/CLEO_AT.2019.JTh2A.60
M3 - Conference contribution
AN - SCOPUS:85068152096
SN - 9781943580576
T3 - Optics InfoBase Conference Papers
BT - CLEO
PB - Optica Publishing Group (formerly OSA)
T2 - CLEO: Applications and Technology, CLEO_AT 2019
Y2 - 5 May 2019 through 10 May 2019
ER -