Heterogeneous Computing Meets Near-Memory Acceleration and High-Level Synthesis in the Post-Moore Era

Nam Sung Kim, Deming Chen, Jinjun Xiong, Wen-Mei W Hwu

Research output: Contribution to journalArticle

Abstract

As the trends driven by Moore's law come to an end, increased heterogeneity at all levels of computing is required to deliver the computing performance needed for emerging applications, leading to the proliferation of various application- or domain-specific accelerators. This in turn demands more memory bandwidth, as heterogeneous computing with accelerators consumes data at a much higher rate than traditional homogeneous computing, limiting the computing performance. To tackle this challenge, this article presents a conceptual near-memory acceleration architecture; demonstrates its practicality and plausibility using a recent experimental platform from IBM, as well as its potential impact on performance and energy efficiency; and discusses the need for adopting a high-level synthesis approach for such a near-memory acceleration architecture. Subsequently, this article concludes with future research directions for broad adoption of near-memory acceleration.

Original languageEnglish (US)
Article number8013455
Pages (from-to)10-18
Number of pages9
JournalIEEE Micro
Volume37
Issue number4
DOIs
StatePublished - Jan 1 2017

Fingerprint

Data storage equipment
Particle accelerators
Energy efficiency
Bandwidth
High level synthesis

Keywords

  • DRAM
  • FPGA
  • compiler technology
  • heterogeneous computing
  • high-level synthesis
  • near-DRAM acceleration

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Heterogeneous Computing Meets Near-Memory Acceleration and High-Level Synthesis in the Post-Moore Era. / Kim, Nam Sung; Chen, Deming; Xiong, Jinjun; Hwu, Wen-Mei W.

In: IEEE Micro, Vol. 37, No. 4, 8013455, 01.01.2017, p. 10-18.

Research output: Contribution to journalArticle

@article{e2d78a97659d4a6ba2ec0845132eec9f,
title = "Heterogeneous Computing Meets Near-Memory Acceleration and High-Level Synthesis in the Post-Moore Era",
abstract = "As the trends driven by Moore's law come to an end, increased heterogeneity at all levels of computing is required to deliver the computing performance needed for emerging applications, leading to the proliferation of various application- or domain-specific accelerators. This in turn demands more memory bandwidth, as heterogeneous computing with accelerators consumes data at a much higher rate than traditional homogeneous computing, limiting the computing performance. To tackle this challenge, this article presents a conceptual near-memory acceleration architecture; demonstrates its practicality and plausibility using a recent experimental platform from IBM, as well as its potential impact on performance and energy efficiency; and discusses the need for adopting a high-level synthesis approach for such a near-memory acceleration architecture. Subsequently, this article concludes with future research directions for broad adoption of near-memory acceleration.",
keywords = "DRAM, FPGA, compiler technology, heterogeneous computing, high-level synthesis, near-DRAM acceleration",
author = "Kim, {Nam Sung} and Deming Chen and Jinjun Xiong and Hwu, {Wen-Mei W}",
year = "2017",
month = "1",
day = "1",
doi = "10.1109/MM.2017.3211105",
language = "English (US)",
volume = "37",
pages = "10--18",
journal = "IEEE Micro",
issn = "0272-1732",
publisher = "IEEE Computer Society",
number = "4",

}

TY - JOUR

T1 - Heterogeneous Computing Meets Near-Memory Acceleration and High-Level Synthesis in the Post-Moore Era

AU - Kim, Nam Sung

AU - Chen, Deming

AU - Xiong, Jinjun

AU - Hwu, Wen-Mei W

PY - 2017/1/1

Y1 - 2017/1/1

N2 - As the trends driven by Moore's law come to an end, increased heterogeneity at all levels of computing is required to deliver the computing performance needed for emerging applications, leading to the proliferation of various application- or domain-specific accelerators. This in turn demands more memory bandwidth, as heterogeneous computing with accelerators consumes data at a much higher rate than traditional homogeneous computing, limiting the computing performance. To tackle this challenge, this article presents a conceptual near-memory acceleration architecture; demonstrates its practicality and plausibility using a recent experimental platform from IBM, as well as its potential impact on performance and energy efficiency; and discusses the need for adopting a high-level synthesis approach for such a near-memory acceleration architecture. Subsequently, this article concludes with future research directions for broad adoption of near-memory acceleration.

AB - As the trends driven by Moore's law come to an end, increased heterogeneity at all levels of computing is required to deliver the computing performance needed for emerging applications, leading to the proliferation of various application- or domain-specific accelerators. This in turn demands more memory bandwidth, as heterogeneous computing with accelerators consumes data at a much higher rate than traditional homogeneous computing, limiting the computing performance. To tackle this challenge, this article presents a conceptual near-memory acceleration architecture; demonstrates its practicality and plausibility using a recent experimental platform from IBM, as well as its potential impact on performance and energy efficiency; and discusses the need for adopting a high-level synthesis approach for such a near-memory acceleration architecture. Subsequently, this article concludes with future research directions for broad adoption of near-memory acceleration.

KW - DRAM

KW - FPGA

KW - compiler technology

KW - heterogeneous computing

KW - high-level synthesis

KW - near-DRAM acceleration

UR - http://www.scopus.com/inward/record.url?scp=85028829304&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85028829304&partnerID=8YFLogxK

U2 - 10.1109/MM.2017.3211105

DO - 10.1109/MM.2017.3211105

M3 - Article

VL - 37

SP - 10

EP - 18

JO - IEEE Micro

JF - IEEE Micro

SN - 0272-1732

IS - 4

M1 - 8013455

ER -