Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning

Joao Ambrosi, Aayush Ankit, Rodrigo Antunes, Sai Rahul Chalamalasetti, Soumitra Chatterjee, Izzat El Hajj, Guilherme Fachini, Paolo Faraboschi, Martin Foltin, Sitao Huang, Wen Mei Hwu, Gustavo Knuppe, Sunil Vishwanathpur Lakshminarasimha, Dejan Milojicic, Mohan Parthasarathy, Filipe Ribeiro, Lucas Rosa, Kaushik Roy, Plinio Silveira, John Paul Strachan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The increasing deployment of machine learning at the core and at the edge for applications such as video and image recognition has resulted in a number of special purpose accelerators in this domain. However, these accelerators do not have full end-to-end software stacks for application development, resulting in hard-to-develop, proprietary, and suboptimal application programming and executables. In this paper, we describe software stack for a memristor-based hybrid (analog-digital)accelerator. The software stack consists of an ONNX converter, an application optimizer, a compiler, a driver, and emulators. The ONNX converter helps leveraging interoperable neural network models developed on frameworks that support ONNX, such as CNTK, Caffe2, Tensorflow, etc. The application optimization layer adapts these interoperable models to the underlying hardware. The compiler generates executable ISA code that the underlying accelerator can run. Finally, the emulator enables software execution without actual hardware which enables hardware design space exploration and testing. By building a software stack, we have made hybrid memristor-based ML accelerators more accessible to software developers, enabled a generation of better-performing executables, and created an environment that can be leveraged by a multitude of existing neural network models developed using other frameworks to target these accelerators.

Original languageEnglish (US)
Title of host publication2018 IEEE International Conference on Rebooting Computing, ICRC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538691700
DOIs
StatePublished - Feb 8 2019
Event2018 IEEE International Conference on Rebooting Computing, ICRC 2018 - Tysons, United States
Duration: Nov 7 2018Nov 9 2018

Publication series

Name2018 IEEE International Conference on Rebooting Computing, ICRC 2018

Conference

Conference2018 IEEE International Conference on Rebooting Computing, ICRC 2018
CountryUnited States
CityTysons
Period11/7/1811/9/18

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ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Ambrosi, J., Ankit, A., Antunes, R., Chalamalasetti, S. R., Chatterjee, S., El Hajj, I., Fachini, G., Faraboschi, P., Foltin, M., Huang, S., Hwu, W. M., Knuppe, G., Lakshminarasimha, S. V., Milojicic, D., Parthasarathy, M., Ribeiro, F., Rosa, L., Roy, K., Silveira, P., & Strachan, J. P. (2019). Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning. In 2018 IEEE International Conference on Rebooting Computing, ICRC 2018 [8638612] (2018 IEEE International Conference on Rebooting Computing, ICRC 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICRC.2018.8638612