@inproceedings{16dfddf0991e43bbb9f73d1a20eaeca3,
title = "Hardware prefetching in bus-based multiprocessors: Pattern characterization and cost-effective hardware",
abstract = "Data prefetching has been widely studied as a technique to hide memory access latency in multiprocessors. Most recent research on hardware prefetching focuses either on uniprocessors, or on distributed shared memory (DSM) and other non bus-based organizations. However, in the context of bus-based SMPs, prefetching poses a number of problems related to the lack of scalability and limited bus bandwidth of these modest-sized machines. This paper considers how the number of processors and the memory access patterns in the program influence the relative performance of sequential and non-sequential prefetching mechanisms in a bus-based SMP. We compare the performance of four inexpensive hardware prefetching techniques, varying the number of processors. After a breakdown of the results based on a performance model, we propose a cost-effective hardware prefetching solution for implementing on such modest-sized multiprocessors.",
author = "Garzar{\'a}n, {M. J.} and Brit, {J. L.} and Ib{\'a}{\~n}ez, {P. E.} and V. Vi{\~n}als",
note = "Publisher Copyright: {\textcopyright} 2001 IEEE.; 9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001 ; Conference date: 07-02-2001 Through 09-02-2001",
year = "2001",
doi = "10.1109/EMPDP.2001.905061",
language = "English (US)",
series = "Proceedings - 9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "345--354",
editor = "Konrad Klockner",
booktitle = "Proceedings - 9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001",
address = "United States",
}