Hardware prefetching in bus-based multiprocessors: Pattern characterization and cost-effective hardware

M. J. Garzarán, J. L. Brit, P. E. Ibáñez, V. Viñals

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Data prefetching has been widely studied as a technique to hide memory access latency in multiprocessors. Most recent research on hardware prefetching focuses either on uniprocessors, or on distributed shared memory (DSM) and other non bus-based organizations. However, in the context of bus-based SMPs, prefetching poses a number of problems related to the lack of scalability and limited bus bandwidth of these modest-sized machines. This paper considers how the number of processors and the memory access patterns in the program influence the relative performance of sequential and non-sequential prefetching mechanisms in a bus-based SMP. We compare the performance of four inexpensive hardware prefetching techniques, varying the number of processors. After a breakdown of the results based on a performance model, we propose a cost-effective hardware prefetching solution for implementing on such modest-sized multiprocessors.

Original languageEnglish (US)
Title of host publicationProceedings - 9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001
EditorsKonrad Klockner
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages345-354
Number of pages10
ISBN (Electronic)0769509878, 9780769509877
DOIs
StatePublished - Jan 1 2001
Externally publishedYes
Event9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001 - Mantova, Italy
Duration: Feb 7 2001Feb 9 2001

Publication series

NameProceedings - 9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001

Other

Other9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001
CountryItaly
CityMantova
Period2/7/012/9/01

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Software
  • Theoretical Computer Science

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