TY - GEN
T1 - Hardware-in-the-loop co-design testbed for flying capacitor multilevel converters
AU - Pallo, Nathan
AU - Foulkes, Thomas
AU - Modeer, Tomas
AU - Fonkwe, Edwin
AU - Gartner, Petar
AU - Pilawa-Podgurski, Robert C.N.
PY - 2017/5/30
Y1 - 2017/5/30
N2 - The multilevel flying capacitor topology is a promising technology for future electric aircraft, where high specific power density power converters are required. Hardware-in-the loop co-design can improve design throughput as more complex implementations of this technology are developed. This paper presents a comparison of hardware-in-the-loop emulation and hardware prototype results for 3-, 5- and 7-level flying capacitor converters. The fidelity of the emulation is investigated for both dc-dc and inverter operation and it is shown that, within certain limits, the converter operation can be emulated closely.
AB - The multilevel flying capacitor topology is a promising technology for future electric aircraft, where high specific power density power converters are required. Hardware-in-the loop co-design can improve design throughput as more complex implementations of this technology are developed. This paper presents a comparison of hardware-in-the-loop emulation and hardware prototype results for 3-, 5- and 7-level flying capacitor converters. The fidelity of the emulation is investigated for both dc-dc and inverter operation and it is shown that, within certain limits, the converter operation can be emulated closely.
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U2 - 10.1109/PECI.2017.7935758
DO - 10.1109/PECI.2017.7935758
M3 - Conference contribution
AN - SCOPUS:85025698005
T3 - 2017 IEEE Power and Energy Conference at Illinois, PECI 2017
BT - 2017 IEEE Power and Energy Conference at Illinois, PECI 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 IEEE Power and Energy Conference at Illinois, PECI 2017
Y2 - 23 February 2017 through 24 February 2017
ER -