Hardware for speculative parallelization of partially-parallel loops in DSM multiprocessors

Research output: Contribution to conferencePaper

Abstract

Hardware-based speculative parallelization of non-analyzable codes on distributed modulo scheduling multiprocessors is challenging. A scheme to parallelize codes that have a modest number of cross-iteration dependences is proposed. Simulation results suggest that the scheme is promising: a 16-processor parallel execution of 4 important loops runs 4.2 and 31 times faster than two different serial executions of the loops.

Original languageEnglish (US)
Pages135-139
Number of pages5
StatePublished - Jan 1 1999
EventProceedings of the 1999 5th International Symposium on High-Performance Computer Architecture, HPCA - Orlando, FL, USA
Duration: Jan 9 1999Jan 13 1999

Other

OtherProceedings of the 1999 5th International Symposium on High-Performance Computer Architecture, HPCA
CityOrlando, FL, USA
Period1/9/991/13/99

ASJC Scopus subject areas

  • Engineering(all)

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    Zhang, Y., Rauchwerger, L., & Torrellas, J. (1999). Hardware for speculative parallelization of partially-parallel loops in DSM multiprocessors. 135-139. Paper presented at Proceedings of the 1999 5th International Symposium on High-Performance Computer Architecture, HPCA, Orlando, FL, USA, .