Hardware-assisted thread and data mapping in hierarchical multicore architectures

Eduardo H.M. Cruz, Matthias Diener, Laércio L. Pilla, Philippe O.A. Navaux

Research output: Contribution to journalArticlepeer-review


The performance and energy efficiency of modern architectures depend on memory locality, which can be improved by thread and data mappings considering the memory access behavior of parallel applications. In this article, we propose intense pages mapping, a mechanism that analyzes the memory access behavior using information about the time the entry of each page resides in the translation lookaside buffer. It provides accurate information with a very low overhead. We present experimental results with simulation and real machines, with average performance improvements of 13.7% and energy savings of 4.4%, which come from reductions in cache misses and interconnection traffic.

Original languageEnglish (US)
Article number28
JournalACM Transactions on Architecture and Code Optimization
Issue number3
StatePublished - Sep 2016
Externally publishedYes


  • Cache memory
  • Communication
  • Data mapping
  • Data sharing
  • NUMA
  • Thread mapping

ASJC Scopus subject areas

  • Software
  • Information Systems
  • Hardware and Architecture


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