Hardware architecture and software stack for PIM based on commercial DRAM technology: Industrial product

Sukhan Lee, Shin Haeng Kang, Jaehoon Lee, Hyeonsu Kim, Eojin Lee, Seungwoo Seo, Hosang Yoon, Seungwon Lee, Kyounghwan Lim, Hyunsung Shin, Jinhyun Kim, O. Seongil, Anand Iyer, David Wang, Kyomin Sohn, Nam Sung Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Emerging applications such as deep neural network demand high off-chip memory bandwidth. However, under stringent physical constraints of chip packages and system boards, it becomes very expensive to further increase the bandwidth of off-chip memory. Besides, transferring data across the memory hierarchy constitutes a large fraction of total energy consumption of systems, and the fraction has steadily increased with the stagnant technology scaling and poor data reuse characteristics of such emerging applications. To cost-effectively increase the bandwidth and energy efficiency, researchers began to reconsider the past processing-in-memory (PIM) architectures and advance them further, especially exploiting recent integration technologies such as 2.5D/3D stacking. Albeit the recent advances, no major memory manufacturer has developed even a proof-of-concept silicon yet, not to mention a product. This is because the past PIM architectures often require changes in host processors and/or application code which memory manufacturers cannot easily govern. In this paper, elegantly tackling the aforementioned challenges, we propose an innovative yet practical PIM architecture. To demonstrate its practicality and effectiveness at the system level, we implement it with a 20nm DRAM technology, integrate it with an unmodified commercial processor, develop the necessary software stack, and run existing applications without changing their source code. Our evaluation at the system level shows that our PIM improves the performance of memory-bound neural network kernels and applications by 11.2× and 3.5×, respectively. Atop the performance improvement, PIM also reduces the energy per bit transfer by 3.5×, and the overall energy efficiency of the system running the applications by 3.2×.

Original languageEnglish (US)
Title of host publicationProceedings - 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture, ISCA 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages43-56
Number of pages14
ISBN (Electronic)9781665433334
DOIs
StatePublished - Jun 2021
Externally publishedYes
Event48th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2021 - Virtual, Online, Spain
Duration: Jun 14 2021Jun 19 2021

Publication series

NameProceedings - International Symposium on Computer Architecture
Volume2021-June
ISSN (Print)1063-6897

Conference

Conference48th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2021
Country/TerritorySpain
CityVirtual, Online
Period6/14/216/19/21

Keywords

  • Accelerator
  • DRAM
  • Neural network
  • Processing in memory

ASJC Scopus subject areas

  • Hardware and Architecture

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