Hardware and software support for speculative execution of sequential binaries on a chip-multiprocessor

Venkata Krishnan, Josep Torrellas

Research output: Contribution to conferencePaper

Abstract

Chip-multiprocessors (CMP) are a promising approach for exploiting the increasing transistor count on a chip. To allow sequential applications to be executed on this architecture, current proposals incorporate hardware support to exploit speculative parallelism. However, these proposals either require re-compilation of the source program or use substantial hardware that tailors the architecture for speculative execution, thereby resulting in wasted resources when running parallel applications. In this paper, we present a CMP architecture that has hardware and software support for speculative execution of sequential binaries without the need for source re-compilation. The software support enables identification of threads from sequential binaries, while a modest amount of hardware allows register-level communication and enforces true inter-thread memory dependences. We evaluate this architecture and show that it is able to deliver high performance.

Original languageEnglish (US)
Pages85-92
Number of pages8
DOIs
StatePublished - 1998
EventProceedings of the 1998 International Conference on Supercomputing - Melbourne, Aust
Duration: Jul 13 1998Jul 17 1998

Other

OtherProceedings of the 1998 International Conference on Supercomputing
CityMelbourne, Aust
Period7/13/987/17/98

ASJC Scopus subject areas

  • Computer Science(all)

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    Krishnan, V., & Torrellas, J. (1998). Hardware and software support for speculative execution of sequential binaries on a chip-multiprocessor. 85-92. Paper presented at Proceedings of the 1998 International Conference on Supercomputing, Melbourne, Aust, . https://doi.org/10.1145/277830.277852