Hardware acceleration of the pair-HMM algorithm for DNA variant calling

Sitao Huang, Gowthami Jayashri Manikandan, Anand Ramachandran, Kyle Rupnow, Wen Mei W. Hwu, Deming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

With the advent of several accurate and sophisticated statistical algorithms and pipelines for DNA sequence analysis, it is becoming increasingly possible to translate raw sequencing data into biologically meaningful information for further clinical analysis and processing. However, given the large volume of the data involved, even modestly complex algorithms would require a prohibitively long time to complete. Hence it is the need of the hour to explore non-conventional implementation platforms to accelerate genomics research. In this work, we present an FPGA-accelerated implementation of the Pair HMM forward algorithm, the performance bottleneck in the HaplotypeCaller, a critical function in the popular GATK variant calling tool. We introduce the PE ring structure which, thanks to the fine-grained parallelism allowed by the FPGA, can be built into various configurations striking a trade-off between instruction-level parallelism (ILP) and data parallelism. We investigate the resource utilization and performance of different configurations. Our solution can achieve a speed-up of up to 487x compared to the C++ baseline implementation on CPU and 1.56? compared to the best published hardware implementation.

Original languageEnglish (US)
Title of host publicationFPGA 2017 - Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
PublisherAssociation for Computing Machinery, Inc
Pages275-284
Number of pages10
ISBN (Electronic)9781450343541
DOIs
StatePublished - Feb 22 2017
Event2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2017 - Monterey, United States
Duration: Feb 22 2017Feb 24 2017

Publication series

NameFPGA 2017 - Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Other

Other2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2017
CountryUnited States
CityMonterey
Period2/22/172/24/17

Keywords

  • Computational genomics
  • FPGA
  • Forward algorithm
  • Hardware acceleration
  • PE ring
  • Pair-HMM

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Huang, S., Manikandan, G. J., Ramachandran, A., Rupnow, K., Hwu, W. M. W., & Chen, D. (2017). Hardware acceleration of the pair-HMM algorithm for DNA variant calling. In FPGA 2017 - Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (pp. 275-284). (FPGA 2017 - Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays). Association for Computing Machinery, Inc. https://doi.org/10.1145/3020078.3021749