TY - GEN
T1 - Hardware acceleration of the pair-HMM algorithm for DNA variant calling
AU - Huang, Sitao
AU - Manikandan, Gowthami Jayashri
AU - Ramachandran, Anand
AU - Rupnow, Kyle
AU - Hwu, Wen Mei W.
AU - Chen, Deming
N1 - Publisher Copyright:
© 2017 ACM.
PY - 2017/2/22
Y1 - 2017/2/22
N2 - With the advent of several accurate and sophisticated statistical algorithms and pipelines for DNA sequence analysis, it is becoming increasingly possible to translate raw sequencing data into biologically meaningful information for further clinical analysis and processing. However, given the large volume of the data involved, even modestly complex algorithms would require a prohibitively long time to complete. Hence it is the need of the hour to explore non-conventional implementation platforms to accelerate genomics research. In this work, we present an FPGA-accelerated implementation of the Pair HMM forward algorithm, the performance bottleneck in the HaplotypeCaller, a critical function in the popular GATK variant calling tool. We introduce the PE ring structure which, thanks to the fine-grained parallelism allowed by the FPGA, can be built into various configurations striking a trade-off between instruction-level parallelism (ILP) and data parallelism. We investigate the resource utilization and performance of different configurations. Our solution can achieve a speed-up of up to 487x compared to the C++ baseline implementation on CPU and 1.56? compared to the best published hardware implementation.
AB - With the advent of several accurate and sophisticated statistical algorithms and pipelines for DNA sequence analysis, it is becoming increasingly possible to translate raw sequencing data into biologically meaningful information for further clinical analysis and processing. However, given the large volume of the data involved, even modestly complex algorithms would require a prohibitively long time to complete. Hence it is the need of the hour to explore non-conventional implementation platforms to accelerate genomics research. In this work, we present an FPGA-accelerated implementation of the Pair HMM forward algorithm, the performance bottleneck in the HaplotypeCaller, a critical function in the popular GATK variant calling tool. We introduce the PE ring structure which, thanks to the fine-grained parallelism allowed by the FPGA, can be built into various configurations striking a trade-off between instruction-level parallelism (ILP) and data parallelism. We investigate the resource utilization and performance of different configurations. Our solution can achieve a speed-up of up to 487x compared to the C++ baseline implementation on CPU and 1.56? compared to the best published hardware implementation.
KW - Computational genomics
KW - FPGA
KW - Forward algorithm
KW - Hardware acceleration
KW - PE ring
KW - Pair-HMM
UR - http://www.scopus.com/inward/record.url?scp=85016014373&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85016014373&partnerID=8YFLogxK
U2 - 10.1145/3020078.3021749
DO - 10.1145/3020078.3021749
M3 - Conference contribution
AN - SCOPUS:85016014373
T3 - FPGA 2017 - Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
SP - 275
EP - 284
BT - FPGA 2017 - Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
PB - Association for Computing Machinery
T2 - 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2017
Y2 - 22 February 2017 through 24 February 2017
ER -