Hardware acceleration for sparse fourier image reconstruction

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Several supercomputer vendors now offer reconfigurable computing (RC) systems, combining general-purpose processors with field-programmable gate arrays (TPGAs). The FPGAs can be configured as custom computing architectures for the computationally intensive parts of each application. In this paper we present an RC-based hardware accelerator for an important medical imaging algorithm: iterative sparse Fourier image reconstruction. We transform the algorithm to exploit massive parallelism available in the FPGA fabric. Our design allows different ways of chaining custom pipelined vector engines, so that different computations can be carried out without reconfiguration overhead. Actual runtime performance data show that we achieve up to 10 times speedup compared to the software-only version. The design is estimated to provide even more speedup on a next-generation RC platform.

Original languageEnglish (US)
Title of host publicationASICON 2007 - 2007 7th International Conference on ASIC Proceeding
Pages1346-1351
Number of pages6
DOIs
StatePublished - Dec 1 2007
Event2007 7th International Conference on ASIC, ASICON 2007 - Guilin, China
Duration: Oct 26 2007Oct 29 2007

Publication series

NameASICON 2007 - 2007 7th International Conference on ASIC Proceeding

Other

Other2007 7th International Conference on ASIC, ASICON 2007
CountryChina
CityGuilin
Period10/26/0710/29/07

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Dinh, Q., Bresler, Y., & Chen, D. (2007). Hardware acceleration for sparse fourier image reconstruction. In ASICON 2007 - 2007 7th International Conference on ASIC Proceeding (pp. 1346-1351). [4415887] (ASICON 2007 - 2007 7th International Conference on ASIC Proceeding). https://doi.org/10.1109/ICASIC.2007.4415887