TY - GEN
T1 - Guilty As Charged
T2 - 22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
AU - Feng, Keven
AU - Vora, Sandeep
AU - Jiang, Rui
AU - Rosenbaum, Elyse
AU - Vasudevan, Shobha
N1 - Funding Information:
This material is based upon work supported by the National Science Foundation under Grant No. 1526106.
Funding Information:
ACKNOWLEDGEMENTS This material is based upon work supported by the National Science Foundation under Grant No. 1526106. The authors would like to thank Mr. O. Girard for design of the open source core and useful discussions. We also thank Dr. Karan Bhatia of Texas Instruments for discussions about microcontroller design.
Publisher Copyright:
© 2019 EDAA.
PY - 2019/5/14
Y1 - 2019/5/14
N2 - Electrostatic discharge (ESD) has been shown to cause severe reliability hazards at the physical level, resulting in permanent and transient errors. We present the first analysis of the effects of ESD-induced errors on instruction-level computation. Our data were measured on a microcontroller test chip fabricated for this study, with discharges from a controlled ESD gun. cosmic-ray-induced soft errors have been widely researched, and modeled as single event upsets (SEUs). Our observations across multiple trials on 3 test chips show that in contrast to radiation-induced errors, ESD can cause much more widespread errors than SEUs. In our trials, we observed system hangs and clock glitches which are serious errors. We also observed errors in the following categories: multiple-bit corruptions across multiple registers, multiple-bit corruptions in the same register, and single-bit corruptions across multiple registers. At the instruction level, these errors manifest as system hangs or serious malfunctioning of I/O operations, interrupt operations, and data/program memory. We demonstrate that ESD-induced errors form a significant reliability threat to higher-level functionality, warranting modeling and mitigation techniques.
AB - Electrostatic discharge (ESD) has been shown to cause severe reliability hazards at the physical level, resulting in permanent and transient errors. We present the first analysis of the effects of ESD-induced errors on instruction-level computation. Our data were measured on a microcontroller test chip fabricated for this study, with discharges from a controlled ESD gun. cosmic-ray-induced soft errors have been widely researched, and modeled as single event upsets (SEUs). Our observations across multiple trials on 3 test chips show that in contrast to radiation-induced errors, ESD can cause much more widespread errors than SEUs. In our trials, we observed system hangs and clock glitches which are serious errors. We also observed errors in the following categories: multiple-bit corruptions across multiple registers, multiple-bit corruptions in the same register, and single-bit corruptions across multiple registers. At the instruction level, these errors manifest as system hangs or serious malfunctioning of I/O operations, interrupt operations, and data/program memory. We demonstrate that ESD-induced errors form a significant reliability threat to higher-level functionality, warranting modeling and mitigation techniques.
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U2 - 10.23919/DATE.2019.8715149
DO - 10.23919/DATE.2019.8715149
M3 - Conference contribution
AN - SCOPUS:85066614716
T3 - Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
SP - 156
EP - 161
BT - Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 25 March 2019 through 29 March 2019
ER -