TY - GEN
T1 - Guard ring interactions and their effect on CMOS latchup resilience
AU - Farbiz, Farzan
AU - Rosenbaum, Elyse
PY - 2008
Y1 - 2008
N2 - Latchup resilience is studied by considering interactions between multiple carrier collectors and N or P-type guard rings. It is shown that P-type taps and guard rings have a deleterious effect on latchup triggered by minority carriers. Physical explanations are provided based on measurements in 90 and 130nm technologies as well as extensive device simulations.
AB - Latchup resilience is studied by considering interactions between multiple carrier collectors and N or P-type guard rings. It is shown that P-type taps and guard rings have a deleterious effect on latchup triggered by minority carriers. Physical explanations are provided based on measurements in 90 and 130nm technologies as well as extensive device simulations.
UR - http://www.scopus.com/inward/record.url?scp=64549126424&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=64549126424&partnerID=8YFLogxK
U2 - 10.1109/IEDM.2008.4796690
DO - 10.1109/IEDM.2008.4796690
M3 - Conference contribution
AN - SCOPUS:64549126424
SN - 9781424423781
T3 - Technical Digest - International Electron Devices Meeting, IEDM
BT - 2008 IEEE International Electron Devices Meeting, IEDM 2008
T2 - 2008 IEEE International Electron Devices Meeting, IEDM 2008
Y2 - 15 December 2008 through 17 December 2008
ER -