Guard ring interactions and their effect on CMOS latchup resilience

Farzan Farbiz, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Latchup resilience is studied by considering interactions between multiple carrier collectors and N or P-type guard rings. It is shown that P-type taps and guard rings have a deleterious effect on latchup triggered by minority carriers. Physical explanations are provided based on measurements in 90 and 130nm technologies as well as extensive device simulations.

Original languageEnglish (US)
Title of host publication2008 IEEE International Electron Devices Meeting, IEDM 2008
DOIs
StatePublished - Dec 1 2008
Event2008 IEEE International Electron Devices Meeting, IEDM 2008 - San Francisco, CA, United States
Duration: Dec 15 2008Dec 17 2008

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Other

Other2008 IEEE International Electron Devices Meeting, IEDM 2008
CountryUnited States
CitySan Francisco, CA
Period12/15/0812/17/08

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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  • Cite this

    Farbiz, F., & Rosenbaum, E. (2008). Guard ring interactions and their effect on CMOS latchup resilience. In 2008 IEEE International Electron Devices Meeting, IEDM 2008 [4796690] (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2008.4796690