TY - GEN
T1 - Graviton
T2 - 17th International Symposium on Applied Reconfigurable Computing, ARC 2021
AU - Dhar, Ashutosh
AU - Reckamp, Paul
AU - Xiong, Jinjun
AU - Hwu, Wen mei
AU - Chen, Deming
N1 - Funding Information:
Acknowledgement. This work was supported by the IBM-ILLINOIS Center for Cognitive Computing Systems Research (C3SR), Xilinx Center of Excellence, and Xilinx Adaptive Compute Clusters (XACC) at the University of Illinois Urbana-Champaign.
Publisher Copyright:
© 2021, Springer Nature Switzerland AG.
PY - 2021
Y1 - 2021
N2 - The rigid organization and distribution of computational and memory resources often limits how well accelerators can cope with changing algorithms and increasing dataset sizes and limits how efficiently they use their computational and memory resources. In this work, we leverage a novel computing paradigm and propose a new memory-based reconfigurable fabric, Graviton. We demonstrate the ability to dynamically trade memory for compute and vice versa, and can tune the architecture of the underlying hardware to suit the memory and compute requirements of the application. On a die-to-die basis, Graviton provides up to 47X more on-chip memory capacity over an Alveo U250 SLR, with just an additional 1.7 % area on a die-to-die basis than modern FPGAs, and is 28.7X faster, on average, on a range of compute and data intensive tasks.
AB - The rigid organization and distribution of computational and memory resources often limits how well accelerators can cope with changing algorithms and increasing dataset sizes and limits how efficiently they use their computational and memory resources. In this work, we leverage a novel computing paradigm and propose a new memory-based reconfigurable fabric, Graviton. We demonstrate the ability to dynamically trade memory for compute and vice versa, and can tune the architecture of the underlying hardware to suit the memory and compute requirements of the application. On a die-to-die basis, Graviton provides up to 47X more on-chip memory capacity over an Alveo U250 SLR, with just an additional 1.7 % area on a die-to-die basis than modern FPGAs, and is 28.7X faster, on average, on a range of compute and data intensive tasks.
KW - Logic folding
KW - Reconfigurable architectures
UR - http://www.scopus.com/inward/record.url?scp=85112643290&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85112643290&partnerID=8YFLogxK
U2 - 10.1007/978-3-030-79025-7_18
DO - 10.1007/978-3-030-79025-7_18
M3 - Conference contribution
AN - SCOPUS:85112643290
SN - 9783030790240
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 254
EP - 264
BT - Applied Reconfigurable Computing. Architectures, Tools, and Applications - 17th International Symposium, ARC 2021, Proceedings
A2 - Derrien, Steven
A2 - Hannig, Frank
A2 - Diniz, Pedro C.
A2 - Chillet, Daniel
PB - Springer
Y2 - 29 June 2021 through 30 June 2021
ER -