Graph partitioning problem for multiple-chip design

Yao Ping Chen, Ting Chi Wang, D. F. Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we introduce a new graph partitioning problem that stems from a multiple-chip design style in which there is a chip library of chips containing predesigned circuit components (e.g. adders, multipliers etc) which are frequently used. Given an arbitrary circuit data flow graph, we have to realize the circuit by appropriately choosing a set of chips from the chip library. In selecting chips from the chip library to realize a given circuit, both the number of chips used and the interconnection cost are to be minimized. Our new graph partitioning problem models this chip selection problem. We present an efficient solution to this problem.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages1778-1781
Number of pages4
ISBN (Print)0780312813
StatePublished - Jan 1 1993
Externally publishedYes
EventProceedings of the 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA
Duration: May 3 1993May 6 1993

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume3
ISSN (Print)0271-4310

Other

OtherProceedings of the 1993 IEEE International Symposium on Circuits and Systems
CityChicago, IL, USA
Period5/3/935/6/93

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Chen, Y. P., Wang, T. C., & Wong, D. F. (1993). Graph partitioning problem for multiple-chip design. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1778-1781). (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3). Publ by IEEE.