### Abstract

In this paper, we introduce a new graph partitioning problem that stems from a multiple-chip design style in which there is a chip library of chips containing predesigned circuit components (e.g. adders, multipliers etc) which are frequently used. Given an arbitrary circuit data flow graph, we have to realize the circuit by appropriately choosing a set of chips from the chip library. In selecting chips from the chip library to realize a given circuit, both the number of chips used and the interconnection cost are to be minimized. Our new graph partitioning problem models this chip selection problem. We present an efficient solution to this problem.

Original language | English (US) |
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Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |

Publisher | Publ by IEEE |

Pages | 1778-1781 |

Number of pages | 4 |

ISBN (Print) | 0780312813 |

State | Published - Jan 1 1993 |

Event | Proceedings of the 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA Duration: May 3 1993 → May 6 1993 |

### Publication series

Name | Proceedings - IEEE International Symposium on Circuits and Systems |
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Volume | 3 |

ISSN (Print) | 0271-4310 |

### Other

Other | Proceedings of the 1993 IEEE International Symposium on Circuits and Systems |
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City | Chicago, IL, USA |

Period | 5/3/93 → 5/6/93 |

### Fingerprint

### ASJC Scopus subject areas

- Electrical and Electronic Engineering

### Cite this

*Proceedings - IEEE International Symposium on Circuits and Systems*(pp. 1778-1781). (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3). Publ by IEEE.

**Graph partitioning problem for multiple-chip design.** / Chen, Yao Ping; Wang, Ting Chi; Wong, D. F.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*Proceedings - IEEE International Symposium on Circuits and Systems.*Proceedings - IEEE International Symposium on Circuits and Systems, vol. 3, Publ by IEEE, pp. 1778-1781, Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, Chicago, IL, USA, 5/3/93.

}

TY - GEN

T1 - Graph partitioning problem for multiple-chip design

AU - Chen, Yao Ping

AU - Wang, Ting Chi

AU - Wong, D. F.

PY - 1993/1/1

Y1 - 1993/1/1

N2 - In this paper, we introduce a new graph partitioning problem that stems from a multiple-chip design style in which there is a chip library of chips containing predesigned circuit components (e.g. adders, multipliers etc) which are frequently used. Given an arbitrary circuit data flow graph, we have to realize the circuit by appropriately choosing a set of chips from the chip library. In selecting chips from the chip library to realize a given circuit, both the number of chips used and the interconnection cost are to be minimized. Our new graph partitioning problem models this chip selection problem. We present an efficient solution to this problem.

AB - In this paper, we introduce a new graph partitioning problem that stems from a multiple-chip design style in which there is a chip library of chips containing predesigned circuit components (e.g. adders, multipliers etc) which are frequently used. Given an arbitrary circuit data flow graph, we have to realize the circuit by appropriately choosing a set of chips from the chip library. In selecting chips from the chip library to realize a given circuit, both the number of chips used and the interconnection cost are to be minimized. Our new graph partitioning problem models this chip selection problem. We present an efficient solution to this problem.

UR - http://www.scopus.com/inward/record.url?scp=0027266191&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027266191&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0027266191

SN - 0780312813

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 1778

EP - 1781

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - Publ by IEEE

ER -