@inproceedings{bf35a5db1717492198f0edc97da6dcf9,
title = "GoldMine: Automatic assertion generation using data mining and static analysis",
abstract = "We present GOLDMINE, a methodology for generating assertions automatically. Our method involves a combination of data mining and static analysis of the Register Transfer Level (RTL) design. We present results of using GoldMine for assertion generation of the RTL of a 1000-core processor design that is still in an evolving stage. Our results show that GoldMine can generate complex, high coverage assertions in RTL, thereby minimizing human effort in this process.",
author = "Shobha Vasudevan and David Sheridan and Sanjay Patel and David Tcheng and Bill Tuohy and Daniel Johnson",
year = "2010",
doi = "10.1109/date.2010.5457129",
language = "English (US)",
isbn = "9783981080162",
series = "Proceedings -Design, Automation and Test in Europe, DATE",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "626--629",
booktitle = "DATE 10 - Design, Automation and Test in Europe",
address = "United States",
note = "Design, Automation and Test in Europe Conference and Exhibition, DATE 2010 ; Conference date: 08-03-2010 Through 12-03-2010",
}