Abstract
We present a methodology to generate goal-oriented test cases for verifying nonlinear analog circuits. We use a learning-based approach to identify the goal regions in circuit's state space. We use the information that we learn to guide the growth of Rapidly-exploring Random Trees (RRTs) towards these goal regions. Compared to previous approaches for test generation, our methodology generates several test cases of the circuit that are more concentrated in the relevant operating regions. We demonstrate the effectiveness of our approach on typical case studies. We show that our methodology can be used to generate test cases for undesirable behavior that was previously hard to detect.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the 49th Annual Design Automation Conference, DAC '12 |
| Pages | 1018-1023 |
| Number of pages | 6 |
| DOIs | |
| State | Published - Jul 11 2012 |
| Event | 49th Annual Design Automation Conference, DAC '12 - San Francisco, CA, United States Duration: Jun 3 2012 → Jun 7 2012 |
Publication series
| Name | Proceedings - Design Automation Conference |
|---|---|
| ISSN (Print) | 0738-100X |
Other
| Other | 49th Annual Design Automation Conference, DAC '12 |
|---|---|
| Country | United States |
| City | San Francisco, CA |
| Period | 6/3/12 → 6/7/12 |
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Keywords
- pre-si testing
- rapidly-exploring random trees
ASJC Scopus subject areas
- Computer Science Applications
- Control and Systems Engineering
- Electrical and Electronic Engineering
- Modeling and Simulation
Cite this
Goal-oriented stimulus generation for analog circuits. / Ahmadyan, Seyed Nematollah; Kumar, Jayanand Asok; Vasudevan, Shobha.
Proceedings of the 49th Annual Design Automation Conference, DAC '12. 2012. p. 1018-1023 (Proceedings - Design Automation Conference).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Goal-oriented stimulus generation for analog circuits
AU - Ahmadyan, Seyed Nematollah
AU - Kumar, Jayanand Asok
AU - Vasudevan, Shobha
PY - 2012/7/11
Y1 - 2012/7/11
N2 - We present a methodology to generate goal-oriented test cases for verifying nonlinear analog circuits. We use a learning-based approach to identify the goal regions in circuit's state space. We use the information that we learn to guide the growth of Rapidly-exploring Random Trees (RRTs) towards these goal regions. Compared to previous approaches for test generation, our methodology generates several test cases of the circuit that are more concentrated in the relevant operating regions. We demonstrate the effectiveness of our approach on typical case studies. We show that our methodology can be used to generate test cases for undesirable behavior that was previously hard to detect.
AB - We present a methodology to generate goal-oriented test cases for verifying nonlinear analog circuits. We use a learning-based approach to identify the goal regions in circuit's state space. We use the information that we learn to guide the growth of Rapidly-exploring Random Trees (RRTs) towards these goal regions. Compared to previous approaches for test generation, our methodology generates several test cases of the circuit that are more concentrated in the relevant operating regions. We demonstrate the effectiveness of our approach on typical case studies. We show that our methodology can be used to generate test cases for undesirable behavior that was previously hard to detect.
KW - pre-si testing
KW - rapidly-exploring random trees
UR - http://www.scopus.com/inward/record.url?scp=84863557236&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84863557236&partnerID=8YFLogxK
U2 - 10.1145/2228360.2228544
DO - 10.1145/2228360.2228544
M3 - Conference contribution
SN - 9781450311991
T3 - Proceedings - Design Automation Conference
SP - 1018
EP - 1023
BT - Proceedings of the 49th Annual Design Automation Conference, DAC '12
ER -