Global wire bus configuration with minimum delay uncertainty

Li Da Huang, Hung Ming Chen, Martin D F Wong

Research output: Contribution to journalConference article

Abstract

The gap between the advances and the utilization of deep submicron (DSM) technology is increasing as the new generation of technology is introduced faster than ever. Signal integrity is one of the most important issues in overcoming this gap. With the increasing coupling capacitance between the high aspect ratio wires, the delay uncertainty is unpredictable in the current design flow. We present an algorithm to generate a global wire bus configuration with minimum delay uncertainty under timing constraints. The timing window information from the timing budget (or specified in IPs) is integrated with modern accurate crosstalk noise models in the proposed algorithm. HSPICE simulations show that the algorithm is very effective and efficient when compared to the buffer insertion scheme with minimum delay. The standard deviation of the delay obtained from the Monte-Carlo simulation is improved by up to 73%. This global wire bus configuration can be adopted in early wire planning to improve the timing closure problem and increase the accuracy of the timing budget.

Original languageEnglish (US)
Article number1253586
Pages (from-to)50-55
Number of pages6
JournalProceedings -Design, Automation and Test in Europe, DATE
DOIs
StatePublished - Dec 1 2003
EventDesign, Automation and Test in Europe Conference and Exhibition, DATE 2003 - Munich, Germany
Duration: Mar 3 2003Mar 7 2003

Fingerprint

Wire
Crosstalk
Aspect ratio
Capacitance
Planning
Uncertainty
Monte Carlo simulation

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Global wire bus configuration with minimum delay uncertainty. / Huang, Li Da; Chen, Hung Ming; Wong, Martin D F.

In: Proceedings -Design, Automation and Test in Europe, DATE, 01.12.2003, p. 50-55.

Research output: Contribution to journalConference article

@article{f1a53584b41d434a997e16bfe2111cc4,
title = "Global wire bus configuration with minimum delay uncertainty",
abstract = "The gap between the advances and the utilization of deep submicron (DSM) technology is increasing as the new generation of technology is introduced faster than ever. Signal integrity is one of the most important issues in overcoming this gap. With the increasing coupling capacitance between the high aspect ratio wires, the delay uncertainty is unpredictable in the current design flow. We present an algorithm to generate a global wire bus configuration with minimum delay uncertainty under timing constraints. The timing window information from the timing budget (or specified in IPs) is integrated with modern accurate crosstalk noise models in the proposed algorithm. HSPICE simulations show that the algorithm is very effective and efficient when compared to the buffer insertion scheme with minimum delay. The standard deviation of the delay obtained from the Monte-Carlo simulation is improved by up to 73{\%}. This global wire bus configuration can be adopted in early wire planning to improve the timing closure problem and increase the accuracy of the timing budget.",
author = "Huang, {Li Da} and Chen, {Hung Ming} and Wong, {Martin D F}",
year = "2003",
month = "12",
day = "1",
doi = "10.1109/DATE.2003.1253586",
language = "English (US)",
pages = "50--55",
journal = "Proceedings -Design, Automation and Test in Europe, DATE",
issn = "1530-1591",

}

TY - JOUR

T1 - Global wire bus configuration with minimum delay uncertainty

AU - Huang, Li Da

AU - Chen, Hung Ming

AU - Wong, Martin D F

PY - 2003/12/1

Y1 - 2003/12/1

N2 - The gap between the advances and the utilization of deep submicron (DSM) technology is increasing as the new generation of technology is introduced faster than ever. Signal integrity is one of the most important issues in overcoming this gap. With the increasing coupling capacitance between the high aspect ratio wires, the delay uncertainty is unpredictable in the current design flow. We present an algorithm to generate a global wire bus configuration with minimum delay uncertainty under timing constraints. The timing window information from the timing budget (or specified in IPs) is integrated with modern accurate crosstalk noise models in the proposed algorithm. HSPICE simulations show that the algorithm is very effective and efficient when compared to the buffer insertion scheme with minimum delay. The standard deviation of the delay obtained from the Monte-Carlo simulation is improved by up to 73%. This global wire bus configuration can be adopted in early wire planning to improve the timing closure problem and increase the accuracy of the timing budget.

AB - The gap between the advances and the utilization of deep submicron (DSM) technology is increasing as the new generation of technology is introduced faster than ever. Signal integrity is one of the most important issues in overcoming this gap. With the increasing coupling capacitance between the high aspect ratio wires, the delay uncertainty is unpredictable in the current design flow. We present an algorithm to generate a global wire bus configuration with minimum delay uncertainty under timing constraints. The timing window information from the timing budget (or specified in IPs) is integrated with modern accurate crosstalk noise models in the proposed algorithm. HSPICE simulations show that the algorithm is very effective and efficient when compared to the buffer insertion scheme with minimum delay. The standard deviation of the delay obtained from the Monte-Carlo simulation is improved by up to 73%. This global wire bus configuration can be adopted in early wire planning to improve the timing closure problem and increase the accuracy of the timing budget.

UR - http://www.scopus.com/inward/record.url?scp=84893731984&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84893731984&partnerID=8YFLogxK

U2 - 10.1109/DATE.2003.1253586

DO - 10.1109/DATE.2003.1253586

M3 - Conference article

AN - SCOPUS:84893731984

SP - 50

EP - 55

JO - Proceedings -Design, Automation and Test in Europe, DATE

JF - Proceedings -Design, Automation and Test in Europe, DATE

SN - 1530-1591

M1 - 1253586

ER -