@inproceedings{c9f6257656db48479869124ab991d84a,
title = "GlitchMap: An FPGA technology mapper for low power considering glitches",
abstract = "In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous poweraware technology mapping algorithms for FPGAs have not taken into account the glitch power reduction. In this paper, we present a dynamic power estimation model and a new technology mapping algorithm considering glitches. To the best of our knowledge, this is the first work that explicitly reduces glitch power during technology mapping for FPGAs. Experiments show that our algorithm, named GlitchMap, is able to reduce dynamic power by 18.7% compared to a previous state-of-the-art power-aware algorithm, EMap [2].",
keywords = "Dynamic power, FPGA technology mapping, Glitch",
author = "Lei Cheng and Deming Chen and Wong, {Martin D.F.}",
year = "2007",
doi = "10.1145/1278480.1278562",
language = "English (US)",
isbn = "1595936270",
series = "Proceedings - Design Automation Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "318--323",
booktitle = "2007 44th ACM/IEEE Design Automation Conference, DAC'07",
address = "United States",
note = "2007 44th ACM/IEEE Design Automation Conference, DAC'07 ; Conference date: 04-06-2007 Through 08-06-2007",
}