GlitchMap: An FPGA technology mapper for low power considering glitches

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous poweraware technology mapping algorithms for FPGAs have not taken into account the glitch power reduction. In this paper, we present a dynamic power estimation model and a new technology mapping algorithm considering glitches. To the best of our knowledge, this is the first work that explicitly reduces glitch power during technology mapping for FPGAs. Experiments show that our algorithm, named GlitchMap, is able to reduce dynamic power by 18.7% compared to a previous state-of-the-art power-aware algorithm, EMap [2].

Original languageEnglish (US)
Title of host publication2007 44th ACM/IEEE Design Automation Conference, DAC'07
Pages318-323
Number of pages6
DOIs
StatePublished - Aug 2 2007
Event2007 44th ACM/IEEE Design Automation Conference, DAC'07 - San Diego, CA, United States
Duration: Jun 4 2007Jun 8 2007

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other2007 44th ACM/IEEE Design Automation Conference, DAC'07
CountryUnited States
CitySan Diego, CA
Period6/4/076/8/07

Keywords

  • Dynamic power
  • FPGA technology mapping
  • Glitch

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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  • Cite this

    Cheng, L., Chen, D., & Wong, M. D. F. (2007). GlitchMap: An FPGA technology mapper for low power considering glitches. In 2007 44th ACM/IEEE Design Automation Conference, DAC'07 (pp. 318-323). [4261198] (Proceedings - Design Automation Conference). https://doi.org/10.1109/DAC.2007.375179