Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration

Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulator-in-a-loop approach. The solutions on this pareto front combined with efficient Monte Carlo approximation ideas are then used to compute the yield-aware pareto fronts. We show experimental results for both the nominal and yield-aware pareto fronts for power and phase noise for a voltage controlled oscillator (VCO) circuit. The presented methodology computes yield-aware pareto fronts in approximately 5-6 times the time required for a single circuit synthesis run and is thus practically efficient. We also show applications of yield-aware paretos to find the optimal VCO circuit to meet the system level specifications of a phase locked loop.

Original languageEnglish (US)
Title of host publication2006 43rd ACM/IEEE Design Automation Conference, DAC'06
Pages31-36
Number of pages6
DOIs
StatePublished - Dec 1 2006

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Keywords

  • Optimization
  • Pareto surfaces
  • Performance space
  • Yield

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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    Tiwary, S. K., Tiwary, P. K., & Rutenbar, R. A. (2006). Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration. In 2006 43rd ACM/IEEE Design Automation Conference, DAC'06 (pp. 31-36). (Proceedings - Design Automation Conference). https://doi.org/10.1145/1146909.1146921