Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration

Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulator-in-a-loop approach. The solutions on this pareto front combined with efficient Monte Carlo approximation ideas are then used to compute the yield-aware pareto fronts. We show experimental results for both the nominal and yield-aware pareto fronts for power and phase noise for a voltage controlled oscillator (VCO) circuit. The presented methodology computes yield-aware pareto fronts in approximately 5-6 times the time required for a single circuit synthesis run and is thus practically efficient. We also show applications of yield-aware paretos to find the optimal VCO circuit to meet the system level specifications of a phase locked loop.

Original languageEnglish (US)
Title of host publication2006 43rd ACM/IEEE Design Automation Conference, DAC'06
Number of pages6
StatePublished - 2006
Externally publishedYes

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


  • Optimization
  • Pareto surfaces
  • Performance space
  • Yield

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering


Dive into the research topics of 'Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration'. Together they form a unique fingerprint.

Cite this