Gate-level information flow security

John Sartori (Inventor), Hari Cherupalli (Inventor), Henry J Duwe (Inventor), Rakesh Kumar (Inventor)

Research output: Patent


A method includes receiving a processor design of a processor, receiving an application to be executed by the processor, and receiving a security policy. The method includes simulating the execution of the application on the processor to identify information flow violations generated by the application based on the security policy.
Original languageEnglish (US)
U.S. patent number11210402
StatePublished - Dec 28 2021

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