GangES: Gang error simulation for hardware resiliency evaluation

Siva Kumar Sastry Hari, Radha Venkatagiri, Sarita V. Adve, Helia Naeimi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As technology scales, the hardware reliability challenge affects a broad computing market, rendering traditional redundancy based solutions too expensive. Software anomaly based hardware error detection has emerged as a low cost reliability solution, but suffers from Silent Data Corruptions (SDCs). It is crucial to accurately evaluate SDC rates and identify SDC producing software locations to develop software-centric low-cost hardware resiliency solutions.

Original languageEnglish (US)
Title of host publication41st Annual International Symposium on Computer Architecture, ISCA 2014 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages61-72
Number of pages12
ISBN (Print)9781479943968
DOIs
StatePublished - 2014
Event2014 ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014 - Minneapolis, MN, United States
Duration: Jun 14 2014Jun 18 2014

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897

Other

Other2014 ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014
Country/TerritoryUnited States
CityMinneapolis, MN
Period6/14/146/18/14

ASJC Scopus subject areas

  • Hardware and Architecture

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