## Abstract

Presented in this paper is a fundamental mathematical basis for power-reduction in VLSI systems. This basis is employed to 1.) derive lower bounds on the power dissipation in digital systems and 2.) unify existing power-reduction techniques under a common framework. The proposed basis is derived from information-theoretic arguments. In particular, a digital signal processing algorithm is viewed as a process of information transfer with an inherent information transfer rate requirement of R bits/sec. Different architectures implementing a given algorithm are equivalent to different communication networks each with a certain capacity C (also in bits/sec). The absolute lower bound on the power dissipation for any given architecture is then obtained by minimizing the signal power such that its channel capacity C is equal to the desired information transfer rate R. Numerical calculations for a simple static CMOS circuit and fundamental basis for the power-reduction capabilities of parallel processing and pipelining are presented.

Original language | English (US) |
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Pages (from-to) | 9-12 |

Number of pages | 4 |

Journal | Proceedings - IEEE International Symposium on Circuits and Systems |

Volume | 4 |

State | Published - Jan 1 1996 |

Event | Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA Duration: May 12 1996 → May 15 1996 |

## ASJC Scopus subject areas

- Electrical and Electronic Engineering