FriendlyFoe: Adversarial Machine Learning as a Practical Architectural Defense Against Side Channel Attacks

Hyoungwook Nam, Raghavendra Pradyumna Pothukuchi, Bo Li, Nam Sung Kim, Josep Torrellas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Machine learning (ML)-based side channel attacks have become prominent threats to computer security. These attacks are often powerful, as ML models easily find patterns in signals. To address this problem, this paper proposes dynamically applying Adversarial Machine Learning (AML) to obfuscate side channels. The rationale is that it has been shown that intelligently injecting an adversarial perturbation can confuse ML classifiers. We call this approach FriendlyFoe and the neural network we introduce to perturb signals FriendlyFoe Defender. FriendlyFoe is a practical, effective, and general architectural technique to obfuscate signals. We show a workflow to design Defenders with low overhead and information leakage, and to customize them for different environments. Defenders are transferable, i.e., they thwart attacker classifiers that are different from those used to train the Defenders. They also resist adaptive attacks, where attackers train using the obfuscated signals collected while the Defender is active. Finally, the approach is general enough to be applicable to different environments. We demonstrate FriendlyFoe against two side channel attacks: one based on memory contention and one on system power. The first example uses a hardware Defender with ns-level response time that, for the same level of security as a Pad-to-Constant scheme, has 27% and 64% lower performance overhead for single- and multi-threaded workloads, respectively. The second example uses a software Defender with ms-level response time that reduces leakage by 3.7 × over a state-of-the-art scheme while reducing the energy overhead by 22.5%.

Original languageEnglish (US)
Title of host publicationPACT 2024 - Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages338-350
Number of pages13
ISBN (Electronic)9798400706318
DOIs
StatePublished - 2024
Event33rd International Conference on Parallel Architectures and Compilation Techniques, PACT 2024 - Long Beach, United States
Duration: Oct 13 2024Oct 16 2024

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
ISSN (Print)1089-795X

Conference

Conference33rd International Conference on Parallel Architectures and Compilation Techniques, PACT 2024
Country/TerritoryUnited States
CityLong Beach
Period10/13/2410/16/24

Keywords

  • Hardware security
  • Machine learning
  • Side-channel analysis

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

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