An apparatus includes parallel delay lines, each exhibiting a delay; a first set of switches for each port of a first set of ports, each of which is to selectively couple a port of the first set of ports to first ends of the delay lines; a second set of switches for each port of a second set of ports, each of which to selectively couple a port of the second set of ports to second ends of the delay lines. A signal source generates a series of clock signals that are sequentially time delayed between the first set of switches and the second set of switches, where an input signal at one of the first or second sets of ports travels back and forth across the first and second sets of delay lines according to activation of the first set and second set of switches until being output.
|Original language||English (US)|
|U.S. patent number||11139851|
|State||Published - Oct 5 2021|