FPGA/DNN co-design: An efficient design methodology for IoT intelligence on the edge

Cong Hao, Xiaofan Zhang, Yuhong Li, Sitao Huang, Jinjun Xiong, Kyle Rupnow, Wen-Mei W Hwu, Deming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

While embedded FPGAs are attractive platforms for DNN acceleration on edge-devices due to their low latency and high energy efficiency, the scarcity of resources of edge-scale FPGA devices also makes it challenging for DNN deployment. In this paper, we propose a simultaneous FPGA/DNN co-design methodology with both bottom-up and top-down approaches: a bottom-up hardwareoriented DNN model search for high accuracy, and a top-down FPGA accelerator design considering DNN-specific characteristics. We also build an automatic co-design flow, including an Auto-DNN engine to perform hardware-oriented DNN model search, as well as an Auto-HLS engine to generate synthesizable C code of the FPGA accelerator for explored DNNs. We demonstrate our co-design approach on an object detection task using PYNQ-Z1 FPGA. Results show that our proposed DNN model and accelerator outperform the state-of-the-art FPGA designs in all aspects including Intersectionover- Union (IoU) (6.2% higher), frames per second (FPS) (2.48× higher), power consumption (40% lower), and energy efficiency (2.5× higher). Compared to GPU-based solutions, our designs deliver similar accuracy but consume far less energy.

Original languageEnglish (US)
Title of host publicationProceedings of the 56th Annual Design Automation Conference 2019, DAC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781450367257
DOIs
StatePublished - Jun 2 2019
Event56th Annual Design Automation Conference, DAC 2019 - Las Vegas, United States
Duration: Jun 2 2019Jun 6 2019

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Conference

Conference56th Annual Design Automation Conference, DAC 2019
CountryUnited States
CityLas Vegas
Period6/2/196/6/19

Fingerprint

Co-design
Field Programmable Gate Array
Design Methodology
Field programmable gate arrays (FPGA)
Accelerator
Particle accelerators
Bottom-up
Energy Efficiency
Energy efficiency
Engine
Engines
Object Detection
Intelligence
Internet of things
High Power
Power Consumption
High Efficiency
High Energy
Latency
High Accuracy

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Cite this

Hao, C., Zhang, X., Li, Y., Huang, S., Xiong, J., Rupnow, K., ... Chen, D. (2019). FPGA/DNN co-design: An efficient design methodology for IoT intelligence on the edge. In Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019 [a206] (Proceedings - Design Automation Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3316781.3317829

FPGA/DNN co-design : An efficient design methodology for IoT intelligence on the edge. / Hao, Cong; Zhang, Xiaofan; Li, Yuhong; Huang, Sitao; Xiong, Jinjun; Rupnow, Kyle; Hwu, Wen-Mei W; Chen, Deming.

Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. a206 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hao, C, Zhang, X, Li, Y, Huang, S, Xiong, J, Rupnow, K, Hwu, W-MW & Chen, D 2019, FPGA/DNN co-design: An efficient design methodology for IoT intelligence on the edge. in Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019., a206, Proceedings - Design Automation Conference, Institute of Electrical and Electronics Engineers Inc., 56th Annual Design Automation Conference, DAC 2019, Las Vegas, United States, 6/2/19. https://doi.org/10.1145/3316781.3317829
Hao C, Zhang X, Li Y, Huang S, Xiong J, Rupnow K et al. FPGA/DNN co-design: An efficient design methodology for IoT intelligence on the edge. In Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. a206. (Proceedings - Design Automation Conference). https://doi.org/10.1145/3316781.3317829
Hao, Cong ; Zhang, Xiaofan ; Li, Yuhong ; Huang, Sitao ; Xiong, Jinjun ; Rupnow, Kyle ; Hwu, Wen-Mei W ; Chen, Deming. / FPGA/DNN co-design : An efficient design methodology for IoT intelligence on the edge. Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (Proceedings - Design Automation Conference).
@inproceedings{e3bc08c3ae3748dc8cd76322772c30a6,
title = "FPGA/DNN co-design: An efficient design methodology for IoT intelligence on the edge",
abstract = "While embedded FPGAs are attractive platforms for DNN acceleration on edge-devices due to their low latency and high energy efficiency, the scarcity of resources of edge-scale FPGA devices also makes it challenging for DNN deployment. In this paper, we propose a simultaneous FPGA/DNN co-design methodology with both bottom-up and top-down approaches: a bottom-up hardwareoriented DNN model search for high accuracy, and a top-down FPGA accelerator design considering DNN-specific characteristics. We also build an automatic co-design flow, including an Auto-DNN engine to perform hardware-oriented DNN model search, as well as an Auto-HLS engine to generate synthesizable C code of the FPGA accelerator for explored DNNs. We demonstrate our co-design approach on an object detection task using PYNQ-Z1 FPGA. Results show that our proposed DNN model and accelerator outperform the state-of-the-art FPGA designs in all aspects including Intersectionover- Union (IoU) (6.2{\%} higher), frames per second (FPS) (2.48× higher), power consumption (40{\%} lower), and energy efficiency (2.5× higher). Compared to GPU-based solutions, our designs deliver similar accuracy but consume far less energy.",
author = "Cong Hao and Xiaofan Zhang and Yuhong Li and Sitao Huang and Jinjun Xiong and Kyle Rupnow and Hwu, {Wen-Mei W} and Deming Chen",
year = "2019",
month = "6",
day = "2",
doi = "10.1145/3316781.3317829",
language = "English (US)",
series = "Proceedings - Design Automation Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019",
address = "United States",

}

TY - GEN

T1 - FPGA/DNN co-design

T2 - An efficient design methodology for IoT intelligence on the edge

AU - Hao, Cong

AU - Zhang, Xiaofan

AU - Li, Yuhong

AU - Huang, Sitao

AU - Xiong, Jinjun

AU - Rupnow, Kyle

AU - Hwu, Wen-Mei W

AU - Chen, Deming

PY - 2019/6/2

Y1 - 2019/6/2

N2 - While embedded FPGAs are attractive platforms for DNN acceleration on edge-devices due to their low latency and high energy efficiency, the scarcity of resources of edge-scale FPGA devices also makes it challenging for DNN deployment. In this paper, we propose a simultaneous FPGA/DNN co-design methodology with both bottom-up and top-down approaches: a bottom-up hardwareoriented DNN model search for high accuracy, and a top-down FPGA accelerator design considering DNN-specific characteristics. We also build an automatic co-design flow, including an Auto-DNN engine to perform hardware-oriented DNN model search, as well as an Auto-HLS engine to generate synthesizable C code of the FPGA accelerator for explored DNNs. We demonstrate our co-design approach on an object detection task using PYNQ-Z1 FPGA. Results show that our proposed DNN model and accelerator outperform the state-of-the-art FPGA designs in all aspects including Intersectionover- Union (IoU) (6.2% higher), frames per second (FPS) (2.48× higher), power consumption (40% lower), and energy efficiency (2.5× higher). Compared to GPU-based solutions, our designs deliver similar accuracy but consume far less energy.

AB - While embedded FPGAs are attractive platforms for DNN acceleration on edge-devices due to their low latency and high energy efficiency, the scarcity of resources of edge-scale FPGA devices also makes it challenging for DNN deployment. In this paper, we propose a simultaneous FPGA/DNN co-design methodology with both bottom-up and top-down approaches: a bottom-up hardwareoriented DNN model search for high accuracy, and a top-down FPGA accelerator design considering DNN-specific characteristics. We also build an automatic co-design flow, including an Auto-DNN engine to perform hardware-oriented DNN model search, as well as an Auto-HLS engine to generate synthesizable C code of the FPGA accelerator for explored DNNs. We demonstrate our co-design approach on an object detection task using PYNQ-Z1 FPGA. Results show that our proposed DNN model and accelerator outperform the state-of-the-art FPGA designs in all aspects including Intersectionover- Union (IoU) (6.2% higher), frames per second (FPS) (2.48× higher), power consumption (40% lower), and energy efficiency (2.5× higher). Compared to GPU-based solutions, our designs deliver similar accuracy but consume far less energy.

UR - http://www.scopus.com/inward/record.url?scp=85067818581&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85067818581&partnerID=8YFLogxK

U2 - 10.1145/3316781.3317829

DO - 10.1145/3316781.3317829

M3 - Conference contribution

AN - SCOPUS:85067818581

T3 - Proceedings - Design Automation Conference

BT - Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

ER -