FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation

Scott Cromar, Jaeho Lee, Deming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Glitches (i.e. spurious signal transitions) are major sources of dynamic power consumption in modern FPGAs. In this paper, we present an FPGA-targeted, glitch-aware, high-level binding algorithm for power and area reduction, accomplished via dynamic power estimation and multiplexer balancing. Our binding algorithm employs a glitch-aware dynamic power estimation technique derived from the FPGA technology mapper in [6]. High-level binding results are converted to VHDL, and synthesized with Altera's Quartus II software, targeting the Cyclone II FPGA architecture. Power characteristics are evaluated with the Altera Power-Play Power Analyzer. The binding results of our algorithm are compared to LOPASS, a state-of-the-art low-power high-level synthesis algorithm for FPGAs. Experimental results show that our algorithm, on average, reduces toggle rate by 22% and area by 9%, resulting in a decrease in dynamic power consumption of 19%. To the best of our knowledge this is the first high-level binding algorithm targeting FP-GAs that considers glitch power.

Original languageEnglish (US)
Title of host publication2009 46th ACM/IEEE Design Automation Conference, DAC 2009
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages838-843
Number of pages6
ISBN (Print)9781605584973
DOIs
StatePublished - 2009
Event2009 46th ACM/IEEE Design Automation Conference, DAC 2009 - San Francisco, CA, United States
Duration: Jul 26 2009Jul 31 2009

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other2009 46th ACM/IEEE Design Automation Conference, DAC 2009
CountryUnited States
CitySan Francisco, CA
Period7/26/097/31/09

Keywords

  • FPGA
  • Glitch power
  • High-level synthesis
  • Power reduction

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

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    Cromar, S., Lee, J., & Chen, D. (2009). FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation. In 2009 46th ACM/IEEE Design Automation Conference, DAC 2009 (pp. 838-843). [5227038] (Proceedings - Design Automation Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/1629911.1630125