Abstract
A new instruction fetch method, forward semantic, is offered to enable the deeply pipelined processors to fetch one useful instruction every cycle. Forward semantic is an improved alternative to the delayed branching (with or without squashing), with five major advantages. Fist, no restriction is imposed on the type of instructions filling the branch slots, which allows a large number of slots to be filled. Second, no modification to the offsets and displacements is necessary when an instruction is copied to fill a branch slot, which simplifies the linker implementation. Third, an interrupted program can resume execution with a single program counter, eliminating the need for reloading the instruction pipeline before resuming execution. Fourth, programs compiled with N slots can execute on pipelines requiring K (K ≤ N) slots, which makes family architecture compatibility possible. Lastly, the filling of branch slots is totally transparent to code compaction and software interlocking schemes. These advantages combine to provide an efficient instruction fetch mechanism and to eliminate artificial penalties on branch cost. At the cost of 11% static code expansion, forward semantic achieves an instruction fetch cost of 1.2 cycles for pipelines requiring 10 slots for each taken branch. This level of instruction fetch efficiency has never been achieved before with conventional instruction fetch methods. The branch cost is dictated by the accuracy of the compile-time branch prediction rather than artificial limitations, such as data dependencies, which prevent the slots from being filled. These results are measured from the execution of real UNIX and CAD programs with complex control structures.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the Annual International Symposium on Microarchitecture, MICRO |
| Editors | Vicki H. Allan |
| Publisher | IEEE Computer Society |
| Pages | 188-198 |
| Number of pages | 11 |
| ISBN (Electronic) | 0897913248 |
| DOIs | |
| State | Published - Aug 1 1989 |
| Event | 22nd Annual Workshop on Microprogramming and Microarchitecture, MICRO 1989 - Dublin, Ireland Duration: Aug 14 1989 → Aug 16 1989 |
Publication series
| Name | Proceedings of the Annual International Symposium on Microarchitecture, MICRO |
|---|---|
| ISSN (Print) | 1072-4451 |
Other
| Other | 22nd Annual Workshop on Microprogramming and Microarchitecture, MICRO 1989 |
|---|---|
| Country | Ireland |
| City | Dublin |
| Period | 8/14/89 → 8/16/89 |
Fingerprint
ASJC Scopus subject areas
- Hardware and Architecture
Cite this
Forward semantic : A compiler-assisted instruction fetch method for heavily pipelined processors. / Chang, Pohua P.; Hwu, Wen-Mei W.
Proceedings of the Annual International Symposium on Microarchitecture, MICRO. ed. / Vicki H. Allan. IEEE Computer Society, 1989. p. 188-198 (Proceedings of the Annual International Symposium on Microarchitecture, MICRO).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Forward semantic
T2 - A compiler-assisted instruction fetch method for heavily pipelined processors
AU - Chang, Pohua P.
AU - Hwu, Wen-Mei W
PY - 1989/8/1
Y1 - 1989/8/1
N2 - A new instruction fetch method, forward semantic, is offered to enable the deeply pipelined processors to fetch one useful instruction every cycle. Forward semantic is an improved alternative to the delayed branching (with or without squashing), with five major advantages. Fist, no restriction is imposed on the type of instructions filling the branch slots, which allows a large number of slots to be filled. Second, no modification to the offsets and displacements is necessary when an instruction is copied to fill a branch slot, which simplifies the linker implementation. Third, an interrupted program can resume execution with a single program counter, eliminating the need for reloading the instruction pipeline before resuming execution. Fourth, programs compiled with N slots can execute on pipelines requiring K (K ≤ N) slots, which makes family architecture compatibility possible. Lastly, the filling of branch slots is totally transparent to code compaction and software interlocking schemes. These advantages combine to provide an efficient instruction fetch mechanism and to eliminate artificial penalties on branch cost. At the cost of 11% static code expansion, forward semantic achieves an instruction fetch cost of 1.2 cycles for pipelines requiring 10 slots for each taken branch. This level of instruction fetch efficiency has never been achieved before with conventional instruction fetch methods. The branch cost is dictated by the accuracy of the compile-time branch prediction rather than artificial limitations, such as data dependencies, which prevent the slots from being filled. These results are measured from the execution of real UNIX and CAD programs with complex control structures.
AB - A new instruction fetch method, forward semantic, is offered to enable the deeply pipelined processors to fetch one useful instruction every cycle. Forward semantic is an improved alternative to the delayed branching (with or without squashing), with five major advantages. Fist, no restriction is imposed on the type of instructions filling the branch slots, which allows a large number of slots to be filled. Second, no modification to the offsets and displacements is necessary when an instruction is copied to fill a branch slot, which simplifies the linker implementation. Third, an interrupted program can resume execution with a single program counter, eliminating the need for reloading the instruction pipeline before resuming execution. Fourth, programs compiled with N slots can execute on pipelines requiring K (K ≤ N) slots, which makes family architecture compatibility possible. Lastly, the filling of branch slots is totally transparent to code compaction and software interlocking schemes. These advantages combine to provide an efficient instruction fetch mechanism and to eliminate artificial penalties on branch cost. At the cost of 11% static code expansion, forward semantic achieves an instruction fetch cost of 1.2 cycles for pipelines requiring 10 slots for each taken branch. This level of instruction fetch efficiency has never been achieved before with conventional instruction fetch methods. The branch cost is dictated by the accuracy of the compile-time branch prediction rather than artificial limitations, such as data dependencies, which prevent the slots from being filled. These results are measured from the execution of real UNIX and CAD programs with complex control structures.
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U2 - 10.1145/75362.75418
DO - 10.1145/75362.75418
M3 - Conference contribution
AN - SCOPUS:84911465782
T3 - Proceedings of the Annual International Symposium on Microarchitecture, MICRO
SP - 188
EP - 198
BT - Proceedings of the Annual International Symposium on Microarchitecture, MICRO
A2 - Allan, Vicki H.
PB - IEEE Computer Society
ER -