Forward error correction for high-speed I/O

Rajan Lakshmi Narasimha, Naresh Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Modern state-of-the-art high-speed (Gb/s) I/O links today rely exclusively upon an equalization-based transceiver to achieve a bit error-rate (BER) of 10-15. This paper explores the potential of applying forward error-correction (FEC) in such links to reduce power and BER. The FEC coding gain can be employed to lower the power consumed in the analog components (e.g., transmit driver, clock recovery unit (CRU)) since these do not scale with process technology. A BER improvement of six orders-of-magnitude and ten orders-of-magnitude is demonstratedfor a 20" FR4 channel operating at 10 Gb/s with a LE and a DFE, respectively, using a BCH code. Savings in the encoderdecoder power overhead of up to 50% is demonstrated for a (63, 36, 11) BCH code using a novel gated decoder architecture.

Original languageEnglish (US)
Title of host publication2008 42nd Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2008
Pages1513-1517
Number of pages5
DOIs
StatePublished - 2008
Event2008 42nd Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2008 - Pacific Grove, CA, United States
Duration: Oct 26 2008Oct 29 2008

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
ISSN (Print)1058-6393

Other

Other2008 42nd Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2008
Country/TerritoryUnited States
CityPacific Grove, CA
Period10/26/0810/29/08

ASJC Scopus subject areas

  • Signal Processing
  • Computer Networks and Communications

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