Formation of Ultra-Shallow Junctions

E. G. Seebauer, P. Gorai

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

The continued rapid and downward scaling of integrated circuits encompasses the p-n junctions that define the source and drain regions of individual transistors. Such junctions are fabricated by ion implantation of dopant atoms, followed by annealing to activate the dopant electrically and remove residual damage to the crystal lattice. These resulting junctions lie close to the surface - presently within a small number of nanometers. Such ultra-shallow junctions (USJs) enhance transistor performance by helping to suppress current leakage and hot carrier effects that become important at small length scales. This chapter summarizes the present state of USJ fabrication technology, along with the technical factors that are driving major changes in methods for both implantation and annealing. The probable impending transition to forming junctions within three-dimensional device structures is also outlined.

Original languageEnglish (US)
Title of host publicationComprehensive Semiconductor Science and Technology
PublisherElsevier Inc.
Pages86-131
Number of pages46
Volume1-6
ISBN (Print)9780444531537
DOIs
StatePublished - Jan 1 2011

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Keywords

  • Annealing
  • Blowup
  • Buried oxide (BOX)
  • Cascading effect
  • Channeling
  • Child-Langmuir law
  • Cluster
  • Complementary metal-oxide-semiconductor (CMOS)
  • Continuous wave (CW)
  • Coulombic force
  • Defect
  • Device scaling
  • Dopant
  • Drain (D)
  • Drain-induced barrier lowering (DIBL)
  • End-of-Range (EOR)
  • Extended defect
  • Fin field effect transistor (finFET)
  • Fowler-Nordheim tunneling
  • Frenkel pair
  • Gas cluster ion beam (GCIB)
  • Gaussian distribution
  • Gettering
  • High-K dielectric (HK)
  • Hot carrier
  • Implantation
  • Intermediate defect configuration (IDC)
  • Interstitial (I)
  • Kick-out
  • LSS theory
  • Leakage current
  • Lower control limit (LCL)
  • Lowly-Doped drain (LDD)
  • Majority carrier
  • Melt laser thermal processing
  • Metal-oxide-semiconductor field effect transistor (MOSFET)
  • Millisecond annealing (MA)
  • Minority carrier
  • Multiple gate field effect transistor (MIGFET)
  • N-type dopant
  • Node
  • Non-melt laser spike annealing
  • Nuclear stopping power
  • Off-current
  • Ostwald ripening
  • P-n junction
  • P-type dopant
  • Pearson-IV
  • Performance index (PI)
  • Plasma doping (PD)
  • Plasma immersion ion implantation (PIII)
  • Plasma immersion ion implantation and deposition (PIII&D)
  • Plasma ion plating (PIL)
  • Plasma source ion implantation (PSII)
  • Pre-amorphization implantation (PAI)
  • Projected range (R)
  • Punch through
  • Pyrometry
  • Random walk
  • Rapid thermal processing (RTP)
  • Retrograde
  • Short channel effects (SCE)
  • Silicon-on-insulator (SOI)
  • Solid-phase epitaxial regrowth (SPER)
  • Source (S)
  • Source/Drain extension (S/D extension)
  • Spike annealing (SA)
  • Statistical process control
  • Straggle (ΔR)
  • Subthreshold region
  • Surface engineering
  • Transient enhanced diffusion
  • Transient enhanced diffusion (TED)
  • Transistor
  • Tunneling
  • Ultra-shallow junction (USJ)
  • Ultra-thin-body (UTB)
  • Upper control limit (UCL)
  • Vacancy (V)
  • Vacancy engineering

ASJC Scopus subject areas

  • Physics and Astronomy(all)

Cite this

Seebauer, E. G., & Gorai, P. (2011). Formation of Ultra-Shallow Junctions. In Comprehensive Semiconductor Science and Technology (Vol. 1-6, pp. 86-131). Elsevier Inc.. https://doi.org/10.1016/B978-0-44-453153-7.00117-6