Formation of Ultra-Shallow Junctions

The continued rapid and downward scaling of integrated circuits encompasses the p-n junctions that define the source and drain regions of individual transistors. Such junctions are fabricated by ion implantation of dopant atoms, followed by annealing to activate the dopant electrically and remove residual damage to the crystal lattice. These resulting junctions lie close to the surface - presently within a small number of nanometers. Such ultra-shallow junctions (USJs) enhance transistor performance by helping to suppress current leakage and hot carrier effects that become important at small length scales. This chapter summarizes the present state of USJ fabrication technology, along with the technical factors that are driving major changes in methods for both implantation and annealing. The probable impending transition to forming junctions within three-dimensional device structures is also outlined.