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Formal performance analysis for faulty MIMO hardware
Jayanand Asok Kumar
, Shobha Vasudevan
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Keyphrases
Register Transfer Level
100%
Formal Performance Analysis
100%
Multiple-input multiple-output
100%
Level Design
75%
Performance Metrics
50%
Probabilistic Model Checking
50%
System Design
25%
Enhanced Approach
25%
Performance Requirements
25%
Communication Systems
25%
Noise Source
25%
Vulnerability
25%
Performance Degradation
25%
Hardware Implementation
25%
Multiple-input multiple-output System
25%
Transient Fault
25%
Permanent Fault
25%
Formal Approach
25%
Complex System Design
25%
Statistical Performance
25%
Probabilistic Temporal Logic
25%
Multiple-input multiple-output Communications
25%
Viterbi Decoder
25%
Diagnostic Properties
25%
Computer Science
Performance Analysis
100%
multiple-input-multiple-output
100%
Register-Transfer Level
100%
Performance Metric
50%
Model Checking
50%
Performance Requirement
25%
Hardware Implementation
25%
Temporal Logic
25%
Performance Degradation
25%
Transient Fault
25%
Permanent Fault
25%
Complex System
25%