This paper describes FOCUS, a simulation environment to conduct fault sensitivity analysis of chip-level designs. The environment can be used to evaluate alternative design tactics at an early design stage where changes can be made at low cost. A range of user specified faults are automatically injected at runtime and their propagation, to the chip I/O pins, is measured through the gate and higher levels. A number of techniques for fault sensitivity analysis are proposed and implemented in the FOCUS environment. These include: transient impact assessment on latch, pin and functional errors, external pin error distribution due to in-chip transients, charge-level sensitivity analysis and, error propagation models to depict the dynamic behavior of latch errors. A design analysis is illustrated with a case study of the impact of transient faults on a microprocessor-based jet-engine controller. The study is used to identify the critical fault propagation paths, the module most sensitive to fault propagation and the module with the highest potential for causing external errors.

Original languageEnglish (US)
Pages (from-to)1515-1526
Number of pages12
JournalIEEE Transactions on Computers
Issue number12
StatePublished - Dec 1992


  • Design for dependability
  • VLSI simulation
  • empirical models
  • error propagation
  • fault injection
  • faults
  • statistical analysis
  • transient

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


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