Floorplanning with power supply noise avoidance

Hung Ming Chen, Li Da Huang, I. Min Liu, Minghorng Lai, D. F. Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution


With today's advanced integrated circuits (ICs) manufacturing technology in the deep submicron (DSM) environment, we can integrate entire electronic systems on a single chip (SoC). However, without careful power supply planning in layout, the design of chips can suffer from mostly signal integrity problems, including IR-drop, ΔI noise, and IC reliability. Post-route methodologies in solving signal integrity problem have been applied but they cause a long turn-around time, which adds costly delays to time-to-market. In this paper, we study the problem of power supply noise avoidance as early as in the floorplanning stage. We show that the noise avoidance in the power supply planning problem can be formulated as a constrained maximum flow problem and present an efficient yet effective heuristic to handle the problem. Experimental results are encouraging. With a slight increase of total wirelength, we achieve almost no IR-drop requirement violation and a 46.6% improvement in ΔI noise constraint violation compared with a previous approach.

Original languageEnglish (US)
Title of host publicationProceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)0780376595
StatePublished - Jan 1 2003
EventAsia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
Duration: Jan 21 2003Jan 24 2003

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC


OtherAsia and South Pacific Design Automation Conference, ASP-DAC 2003

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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