TY - GEN
T1 - Floorplanning with power supply noise avoidance
AU - Chen, Hung Ming
AU - Huang, Li Da
AU - Liu, I. Min
AU - Lai, Minghorng
AU - Wong, D. F.
N1 - Publisher Copyright:
© 2003 IEEE.
PY - 2003
Y1 - 2003
N2 - With today's advanced integrated circuits (ICs) manufacturing technology in the deep submicron (DSM) environment, we can integrate entire electronic systems on a single chip (SoC). However, without careful power supply planning in layout, the design of chips can suffer from mostly signal integrity problems, including IR-drop, ΔI noise, and IC reliability. Post-route methodologies in solving signal integrity problem have been applied but they cause a long turn-around time, which adds costly delays to time-to-market. In this paper, we study the problem of power supply noise avoidance as early as in the floorplanning stage. We show that the noise avoidance in the power supply planning problem can be formulated as a constrained maximum flow problem and present an efficient yet effective heuristic to handle the problem. Experimental results are encouraging. With a slight increase of total wirelength, we achieve almost no IR-drop requirement violation and a 46.6% improvement in ΔI noise constraint violation compared with a previous approach.
AB - With today's advanced integrated circuits (ICs) manufacturing technology in the deep submicron (DSM) environment, we can integrate entire electronic systems on a single chip (SoC). However, without careful power supply planning in layout, the design of chips can suffer from mostly signal integrity problems, including IR-drop, ΔI noise, and IC reliability. Post-route methodologies in solving signal integrity problem have been applied but they cause a long turn-around time, which adds costly delays to time-to-market. In this paper, we study the problem of power supply noise avoidance as early as in the floorplanning stage. We show that the noise avoidance in the power supply planning problem can be formulated as a constrained maximum flow problem and present an efficient yet effective heuristic to handle the problem. Experimental results are encouraging. With a slight increase of total wirelength, we achieve almost no IR-drop requirement violation and a 46.6% improvement in ΔI noise constraint violation compared with a previous approach.
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U2 - 10.1109/ASPDAC.2003.1195053
DO - 10.1109/ASPDAC.2003.1195053
M3 - Conference contribution
AN - SCOPUS:84954410160
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 427
EP - 430
BT - Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Asia and South Pacific Design Automation Conference, ASP-DAC 2003
Y2 - 21 January 2003 through 24 January 2003
ER -