Floorplanning for low power designs

Kai Yuan Chao, D. F. Wong

Research output: Contribution to journalConference articlepeer-review


In this paper, a floorplanner for low power designs is presented. Our objective is to optimize total power consumption and area during the selection and placement of circuit modules. Furthermore, our method considers the reduction of power line noises, thermal reliability problems, and performance requirements.

Original languageEnglish (US)
Pages (from-to)45-48
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 1995
Externally publishedYes
EventProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
Duration: Apr 30 1995May 3 1995

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'Floorplanning for low power designs'. Together they form a unique fingerprint.

Cite this