Abstract
In this paper, a floorplanner for low power designs is presented. Our objective is to optimize total power consumption and area during the selection and placement of circuit modules. Furthermore, our method considers the reduction of power line noises, thermal reliability problems, and performance requirements.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 45-48 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 1 |
| State | Published - 1995 |
| Externally published | Yes |
| Event | Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA Duration: Apr 30 1995 → May 3 1995 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering