Floorplan design of VLSI circuits

D. F. Wong, C. L. Liu

Research output: Contribution to journalArticlepeer-review


In this paper we present two algorithms for the floorplan design problem. The algorithms are quite similar in spirit. They both use Polish expressions to represent floorplans and employ the search method of simulated annealing. The first algorithm is for the case where all modules are rectangular, and the second one is for the case where the modules are either rectangular or L-shaped. Our algorithms consider simultaneously the interconnection information as well as the area and shape information for the modules. Experimental results indicate that our algorithms perform well for many test problems.

Original languageEnglish (US)
Pages (from-to)263-291
Number of pages29
Issue number1-4
StatePublished - Jun 1989
Externally publishedYes


  • Floorplan design
  • Simulated annealing
  • VLSI circuit layout

ASJC Scopus subject areas

  • Computer Science(all)
  • Computer Science Applications
  • Applied Mathematics


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