FlexiCores: Low Footprint, High Yield, Field Reprogrammable Flexible Microprocessors

Nathaniel Bleier, Calvin Lee, Francisco Rodriguez, Antony Sou, Scott White, Rakesh Kumar

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Flexible electronics is a promising approach to target applications whose computational needs are not met by traditional silicon-based electronics due to their conformality, thinness, or cost requirements. A microprocessor is a critical component for many such applications; however, it is unclear whether it is feasible to build flexible processors at scale (i.e., at high yield), since very few flexible microprocessors have been reported and no yield data or data from multiple chips has been reported. Also, prior manufactured flexible systems were not feld-reprogrammable and were evaluated either on a simple set of test vectors or a single program. A working flexible microprocessor chip supporting complex or multiple applications has not been demonstrated. Finally, no prior work performs a design space of flexible microprocessors to optimize area, code size, and energy of such microprocessors. In this work, we fabricate and test hundreds of FlexiCores-flexible 0.8 µ m IGZO TFT-based feld-reprogrammable 4 and 8-bit microprocessor chips optimized for low footprint and yield. We show that these gate count-optimized processors can have high yield (4-bit FlexiCores have 81% yield-sufcient to enable subcent cost if produced at volume). We evaluate these chips over a suite of representative kernels-the kernels take 4.28 ms to 12.9 ms and 21.0 µ J to 61.4 µ J for execution (at 360 nJ per instruction). We also present the frst characterization of process variation for a flexible processor-we observe signifcant process variation (relative standard deviation of 15.3% and 21.5% in terms of current draw of 4-bit and 8-bit FlexiCore chips respectively). Finally, we perform a design space exploration and identify design points much better than FlexiCores-the new cores consume only 45-56% the energy of the base design, and have code size less than 30% of the base design, with an area overhead of 9-37%.

Original languageEnglish (US)
Title of host publicationISCA 2022 - Proceedings of the 49th Annual International Symposium on Computer Architecture
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages16
ISBN (Electronic)9781450386104
StatePublished - Jun 18 2022
Event49th IEEE/ACM International Symposium on Computer Architecture, ISCA 2022 - New York, United States
Duration: Jun 18 2022Jun 22 2022

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897


Conference49th IEEE/ACM International Symposium on Computer Architecture, ISCA 2022
Country/TerritoryUnited States
CityNew York

ASJC Scopus subject areas

  • Hardware and Architecture


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