TY - JOUR
T1 - Fin Design Topology Optimization for Direct Liquid Cooling of Multichip Power Modules
AU - Lad, Aniket Ajay
AU - Roman, Eric
AU - Zhao, Yue
AU - King, William P.
AU - Miljkovic, Nenad
N1 - This work was supported in part by the Power Optimization of Electro-Thermal Systems (POETS) National Science Foundation Engineering Research Center under Agreement EEC-1449548 and in part by the Advanced Research Project Agency-Energy (ARPA-E) under Agreement DE-AR0000895. The work of Nenad Miljkovic was support by the International Institute for Carbon Neutral Energy Research under Grant WPI-I2CNER through the Japanese Ministry of Education, Culture, Sports, Science and Technology.
PY - 2024/5/1
Y1 - 2024/5/1
N2 - This article demonstrates the use of topology optimization (TO) to generate optimal fin designs capable of high heat flux removal without increasing the pumping power. We use pseudo-3-D modeling validated against 3-D simulations for thermal-hydraulic performance, which reduces the computational intensity and allows for a wider range of designs to be considered. The accuracy of the pseudo-3-D modeling is aided by allowing the heat transfer coefficient to vary locally with the flow conditions, in contrast to other studies that often assume constant heat transfer coefficient independent of surface shape. We generated TO designs with density fields representing six different conventional fin designs, including straight, zigzag, and pin fins of different dimensions along with the traditional constant intermediate density field. TO designs outperformed their conventional counterparts by delivering lower chip temperatures for similar or lower pressure drops at a fixed flow rate. In addition to the lower chip temperatures, the difference of average temperatures for the chip rows along the flow direction was 76.3% lower on average for the TO designs compared to the conventional designs. We produced and tested prototype finned base plates using conventional straight fin design and a TO design, which showed similar pressure drop to the straight fin design in 3-D simulations. Heating was provided using ceramic resistor chips as surrogates for power semiconductor devices. Experimental testing validated the predictions for device temperatures and pressure drops. The experiments demonstrate the effectiveness of the TO design, which gave a 12.3% (from 0.47 °C.cm2/W to 0.41 °C.cm2/W) reduction in thermal resistance and 81.8% (from 2.75 °C to 0.49 °C) lower difference in chip temperatures along the flow direction compared to the conventional design. The performance improvements were consistent for the range of flow rates in laminar flow regime, for which the optimization was performed as well as turbulent flow regime.
AB - This article demonstrates the use of topology optimization (TO) to generate optimal fin designs capable of high heat flux removal without increasing the pumping power. We use pseudo-3-D modeling validated against 3-D simulations for thermal-hydraulic performance, which reduces the computational intensity and allows for a wider range of designs to be considered. The accuracy of the pseudo-3-D modeling is aided by allowing the heat transfer coefficient to vary locally with the flow conditions, in contrast to other studies that often assume constant heat transfer coefficient independent of surface shape. We generated TO designs with density fields representing six different conventional fin designs, including straight, zigzag, and pin fins of different dimensions along with the traditional constant intermediate density field. TO designs outperformed their conventional counterparts by delivering lower chip temperatures for similar or lower pressure drops at a fixed flow rate. In addition to the lower chip temperatures, the difference of average temperatures for the chip rows along the flow direction was 76.3% lower on average for the TO designs compared to the conventional designs. We produced and tested prototype finned base plates using conventional straight fin design and a TO design, which showed similar pressure drop to the straight fin design in 3-D simulations. Heating was provided using ceramic resistor chips as surrogates for power semiconductor devices. Experimental testing validated the predictions for device temperatures and pressure drops. The experiments demonstrate the effectiveness of the TO design, which gave a 12.3% (from 0.47 °C.cm2/W to 0.41 °C.cm2/W) reduction in thermal resistance and 81.8% (from 2.75 °C to 0.49 °C) lower difference in chip temperatures along the flow direction compared to the conventional design. The performance improvements were consistent for the range of flow rates in laminar flow regime, for which the optimization was performed as well as turbulent flow regime.
KW - Convection heat transfer
KW - direct cooling
KW - power electronics thermal management
KW - topology optimization (TO)
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U2 - 10.1109/TCPMT.2024.3363050
DO - 10.1109/TCPMT.2024.3363050
M3 - Article
AN - SCOPUS:85184798556
SN - 2156-3950
VL - 14
SP - 795
EP - 809
JO - IEEE Transactions on Components, Packaging and Manufacturing Technology
JF - IEEE Transactions on Components, Packaging and Manufacturing Technology
IS - 5
ER -