Field-testing IMPACT EPIC research results in Itanium 2

John W. Sias, Sain Zee Ueng, Geoff A. Kent, Ian M. Steiner, Wen Mei W. Hwu

Research output: Contribution to journalConference article

Abstract

Explicitly-Parallel Instruction Computing (EPIC) provides architectural features, including predication and explicit control speculation, intended to enhance the compiler's ability to expose instruction-level parallelism (ILP) in control-intensive programs. Aggressive structural transformations using these features, though described in the literature, have not yet been fully characterized in complete systems. Using the Intel Itanium 2 microprocessor, the SPECint2000 benchmarks and the IMPACT Compiler for IA-64, a research compiler competitive with the best commercial compilers on the platform, we provide an in situ evaluation of code generated using aggressive, EPIC-enabled techniques in a reality-constrained microarchitecture. Our work shows a 1.13 average speedup (up to 1.50) due to these compilation techniques, relative to traditionally-optimized code at the same inlining and pointer analysis levels, and a 1.55 speedup (up to 2.30) relative to GNU GCC, a solid traditional compiler. Detailed results show that the structural compilation approach provides benefits far beyond a decrease in branch misprediction penalties and that it both positively and negatively impacts instruction cache performance. We also demonstrate the increasing significance of runtime effects, such as data cache and TLB, in determining end performance and the interaction of these effects with control speculation.

Original languageEnglish (US)
Pages (from-to)26-37
Number of pages12
JournalConference Proceedings - Annual International Symposium on Computer Architecture, ISCA
Volume31
StatePublished - Oct 8 2004
EventProceedings -31st Annual International Symposium on Computer Architecture - Munich, Germany
Duration: Jun 19 2004Jun 23 2004

ASJC Scopus subject areas

  • Hardware and Architecture

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