FEC-based 4 Gb/s backplane transceiver in 90nm CMOS

Adam C. Faust; Rajan Lakshmi Narasimha; Karan Bhatia; Ankit Srivastava; Chhay Kong; Hyeon Min Bae; Elyse Rosenbaum; Naresh Shanbhag

doi:10.1109/CICC.2012.6330665

FEC-based 4 Gb/s backplane transceiver in 90nm CMOS

Adam C. Faust, Rajan Lakshmi Narasimha, Karan Bhatia, Ankit Srivastava, Chhay Kong, Hyeon Min Bae, Elyse Rosenbaum, Naresh Shanbhag

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents the first reported design of a forward error correction (FEC)-based high-speed serial link. A 4 Gb/s line rate transceiver in 90nm CMOS is designed with short block length BCH codes. FEC is shown to be effective for high code rates, high information rates and low SNR channels. Measurement results of the transceiver over a 18.2 dB Nyquist loss channel show a 45x reduction in minimum BER, and an increase in jitter tolerance at low transmit swings. For a BER ≤ 10^-12, the addition of FEC reduces the required transmit signal swing, from approximately 0.75 V_ppd to less than 0.5 V_ppd.

Original language	English (US)
Title of host publication	Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012
DOIs	https://doi.org/10.1109/CICC.2012.6330665
State	Published - 2012
Event	34th Annual Custom Integrated Circuits Conference, CICC 2012 - San Jose, CA, United States Duration: Sep 9 2012 → Sep 12 2012

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Other

Other	34th Annual Custom Integrated Circuits Conference, CICC 2012
Country/Territory	United States
City	San Jose, CA
Period	9/9/12 → 9/12/12

Keywords

Forward Error Correction
High-Speed Serial Link

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/CICC.2012.6330665

Library availability

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Faust, A. C., Narasimha, R. L., Bhatia, K., Srivastava, A., Kong, C., Bae, H. M., Rosenbaum, E., & Shanbhag, N. (2012). FEC-based 4 Gb/s backplane transceiver in 90nm CMOS. In Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012 Article 6330665 (Proceedings of the Custom Integrated Circuits Conference). https://doi.org/10.1109/CICC.2012.6330665

Faust, AC, Narasimha, RL, Bhatia, K, Srivastava, A, Kong, C, Bae, HM, Rosenbaum, E & Shanbhag, N 2012, FEC-based 4 Gb/s backplane transceiver in 90nm CMOS. in Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012., 6330665, Proceedings of the Custom Integrated Circuits Conference, 34th Annual Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, United States, 9/9/12. https://doi.org/10.1109/CICC.2012.6330665

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title = "FEC-based 4 Gb/s backplane transceiver in 90nm CMOS",

abstract = "This paper presents the first reported design of a forward error correction (FEC)-based high-speed serial link. A 4 Gb/s line rate transceiver in 90nm CMOS is designed with short block length BCH codes. FEC is shown to be effective for high code rates, high information rates and low SNR channels. Measurement results of the transceiver over a 18.2 dB Nyquist loss channel show a 45x reduction in minimum BER, and an increase in jitter tolerance at low transmit swings. For a BER ≤ 10-12, the addition of FEC reduces the required transmit signal swing, from approximately 0.75 Vppd to less than 0.5 Vppd.",

keywords = "Forward Error Correction, High-Speed Serial Link",

author = "Faust, {Adam C.} and Narasimha, {Rajan Lakshmi} and Karan Bhatia and Ankit Srivastava and Chhay Kong and Bae, {Hyeon Min} and Elyse Rosenbaum and Naresh Shanbhag",

year = "2012",

doi = "10.1109/CICC.2012.6330665",

language = "English (US)",

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series = "Proceedings of the Custom Integrated Circuits Conference",

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AU - Faust, Adam C.

AU - Narasimha, Rajan Lakshmi

AU - Bhatia, Karan

AU - Srivastava, Ankit

AU - Kong, Chhay

AU - Bae, Hyeon Min

AU - Rosenbaum, Elyse

AU - Shanbhag, Naresh

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N2 - This paper presents the first reported design of a forward error correction (FEC)-based high-speed serial link. A 4 Gb/s line rate transceiver in 90nm CMOS is designed with short block length BCH codes. FEC is shown to be effective for high code rates, high information rates and low SNR channels. Measurement results of the transceiver over a 18.2 dB Nyquist loss channel show a 45x reduction in minimum BER, and an increase in jitter tolerance at low transmit swings. For a BER ≤ 10-12, the addition of FEC reduces the required transmit signal swing, from approximately 0.75 Vppd to less than 0.5 Vppd.

AB - This paper presents the first reported design of a forward error correction (FEC)-based high-speed serial link. A 4 Gb/s line rate transceiver in 90nm CMOS is designed with short block length BCH codes. FEC is shown to be effective for high code rates, high information rates and low SNR channels. Measurement results of the transceiver over a 18.2 dB Nyquist loss channel show a 45x reduction in minimum BER, and an increase in jitter tolerance at low transmit swings. For a BER ≤ 10-12, the addition of FEC reduces the required transmit signal swing, from approximately 0.75 Vppd to less than 0.5 Vppd.

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KW - High-Speed Serial Link

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T2 - 34th Annual Custom Integrated Circuits Conference, CICC 2012

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FEC-based 4 Gb/s backplane transceiver in 90nm CMOS

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