FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs

Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen Mei W. Hwu

Research output: Chapter in Book/Report/Conference proceedingConference contribution


As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore's law, the computing industry has switched its route to higher performance through parallel processing. The rise of multi-core systems in all domains of computing has opened the door to heterogeneous multi-processors, where processors of different compute characteristics can be combined to effectively boost the performance per watt of different application kernels. GPUs and FPGAs are becoming very popular in PC-based heterogeneous systems for speeding up compute intensive kernels of scientific, imaging and simulation applications. GPUs can execute hundreds of concurrent threads, while FPGAs provide customized concurrency for highly parallel kernels. However, exploiting the parallelism available in these applications is currently not a push-button task. Often the programmer has to expose the application's fine and coarse grained parallelism by using special APIs. CUDA is such a parallel-computing API that is driven by the GPU industry and is gaining significant popularity. In this work, we adapt the CUDA programming model into a new FPGA design flow called FCUDA, which efficiently maps the coarse and fine grained parallelism exposed in CUDA onto the reconfigurable fabric. Our CUDA-to-FPGA flow employs AutoPilot, an advanced high-level synthesis tool which enables high-abstraction FPGA programming. FCUDA is based on a source-to-source compilation that transforms the SPMD CUDA thread blocks into parallel C code for AutoPilot. We describe the details of our CUDA-to-FPGA flow and demonstrate the highly competitive performance of the resulting customized FPGA multi-core accelerators. To the best of our knowledge, this is the first CUDA-to-FPGA flow to demonstrate the applicability and potential advantage of using the CUDAprogramming model for high-performance computing in FPGAs.

Original languageEnglish (US)
Title of host publication2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009
Number of pages8
StatePublished - 2009
Event2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009 - San Francisco, CA, United States
Duration: Jul 27 2009Jul 28 2009

Publication series

Name2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009


Other2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009
Country/TerritoryUnited States
CitySan Francisco, CA

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture


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