Fault-tolerant routing algorithms in networks on-chip

Reyhaneh Jabbarvand Behrouz, Mehdi Modarressi, Hamid Sarbazi-Azad

Research output: Chapter in Book/Report/Conference proceedingChapter


As the semiconductor industry advances to the deep sub-micron and nano technology points, the on-chip components are more prone to the defects during manufacturing and faults during system life time. These components include the Networks-on-Chip (NoCs) which are expected to be an important part of the future complex multi-core and many-core chips. As a result, fault tolerant techniques are essential to improve the yield of modern complex chips. In this chapter, we propose a fault-tolerant routing algorithm that keeps the negative effect of faulty components on the NoC power and performance as low as possible. Targeting intermittent faults, we achieve fault tolerance by employing a simple and fast mechanism composed of two processes: NoC monitoring and route adaption. The former keeps the track of the on-chip traffic pattern and faulty links, whereas the latter adapts the packet paths to the current set of faulty components. This mechanism exploits the global information of the state of the NoC components and on-chip traffic pattern and aims to minimize the performance loss and the power overhead imposed by the faulty NoC links and nodes. Experimental results show the effectiveness of the proposed technique, in that it offers lower average message latency and power consumption and a higher reliability, compared to some state-of-the art related work.

Original languageEnglish (US)
Title of host publicationRouting Algorithms in Networks-on-Chip
EditorsMaurizio Palesi, Masoud Daneshtalab
Number of pages18
ISBN (Electronic)9781461482741
ISBN (Print)1461482739, 9781461482734
StatePublished - Apr 1 2014
Externally publishedYes


  • Routing Algorithm
  • Virtual Channel (VC)
  • Intermittent Faults
  • Average Message Latency (AML)
  • Faulty Links

ASJC Scopus subject areas

  • General Engineering

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