FAULT CHARACTERIZATION AND DELAY FAULT TESTING OF GAAS LOGIC CIRCUITS.

Brian T. Cunningham, W. Kent Fuchs, Prithviraj Banerjee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The results are presented of one simulation-based fault characterization study for two classes of high electron mobility transistor GaAs logic circuits, and an approach to testing one class of functional faults of particular importance to GaAs circuits is provided. The fault characterization study indicates that the GaAs logic circuits are highly susceptible to faults resulting in timing errors. On the basis of the fault characterization results, a timing algebra test generation strategy is developed for detection of failures causing timing errors. The strategy is appropriate for detection of gate-level path faults as well as transistor-level branch faults.

Original languageEnglish (US)
Title of host publicationDigest of Papers - International Test Conference
PublisherIEEE
Pages836-842
Number of pages7
ISBN (Print)081860798X
StatePublished - Dec 1 1987
EventDig Pap Int Test Conf 1987, Proc, Integr of Test with Des and Manuf - Washington, DC, USA
Duration: Sep 1 1987Sep 3 1987

Publication series

NameDigest of Papers - International Test Conference
ISSN (Print)0743-1686

Other

OtherDig Pap Int Test Conf 1987, Proc, Integr of Test with Des and Manuf
CityWashington, DC, USA
Period9/1/879/3/87

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Cunningham, B. T., Fuchs, W. K., & Banerjee, P. (1987). FAULT CHARACTERIZATION AND DELAY FAULT TESTING OF GAAS LOGIC CIRCUITS. In Digest of Papers - International Test Conference (pp. 836-842). (Digest of Papers - International Test Conference). IEEE.