TY - GEN
T1 - FAULT CHARACTERIZATION AND DELAY FAULT TESTING OF GAAS LOGIC CIRCUITS.
AU - Cunningham, Brian T.
AU - Fuchs, W. Kent
AU - Banerjee, Prithviraj
PY - 1987
Y1 - 1987
N2 - The results are presented of one simulation-based fault characterization study for two classes of high electron mobility transistor GaAs logic circuits, and an approach to testing one class of functional faults of particular importance to GaAs circuits is provided. The fault characterization study indicates that the GaAs logic circuits are highly susceptible to faults resulting in timing errors. On the basis of the fault characterization results, a timing algebra test generation strategy is developed for detection of failures causing timing errors. The strategy is appropriate for detection of gate-level path faults as well as transistor-level branch faults.
AB - The results are presented of one simulation-based fault characterization study for two classes of high electron mobility transistor GaAs logic circuits, and an approach to testing one class of functional faults of particular importance to GaAs circuits is provided. The fault characterization study indicates that the GaAs logic circuits are highly susceptible to faults resulting in timing errors. On the basis of the fault characterization results, a timing algebra test generation strategy is developed for detection of failures causing timing errors. The strategy is appropriate for detection of gate-level path faults as well as transistor-level branch faults.
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M3 - Conference contribution
AN - SCOPUS:0023589517
SN - 081860798X
T3 - Digest of Papers - International Test Conference
SP - 836
EP - 842
BT - Digest of Papers - International Test Conference
PB - IEEE
T2 - Dig Pap Int Test Conf 1987, Proc, Integr of Test with Des and Manuf
Y2 - 1 September 1987 through 3 September 1987
ER -