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Fast timing simulation for submicron hot-carrier degradation
Weishi Sun
,
Elyse Rosenbaum
, Sung Mo Kang
Electrical and Computer Engineering
Coordinated Science Lab
Research output
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peer-review
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Keyphrases
Transistor
100%
Submicron
100%
Time-dependent Simulation
100%
Hot Carrier Degradation
100%
Fast Timing
100%
Hot Carriers
50%
Quadratic Model
50%
I-V Curve
50%
Quasi-static Model
50%
CMOS Integrated Circuits
50%
Time-dependent Reliability
50%
NMOS
50%
PMOS
50%
Very Large Integrated Circuits
50%
Engineering
Current-Voltage Characteristic
100%
CMOS Integrated Circuits
100%
Static Model
100%
Integrated Circuit
100%
Material Science
Hot Carrier
100%
Transistor
66%
Electronic Circuit
66%
Current-Voltage Characteristic
33%
Computer Science
Timing Simulation
100%
Integrated Circuit
100%
Quadratic Model
50%