Fast placement optimization of power supply pads

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Power grid networks in VLSI circuits are required to provide adequate input supply to ensure reliable performance. In this paper, we propose algorithms to find the placement of power pads that minimize not only the worst voltage drop but also the voltage deviation across the power grid. Our algorithm uses simulated annealing to minimize the total cost of voltage drops. The key enabler for efficient optimization is a fast localized node-based iterative method to compute the voltages after each movement of pads. Experimental results show that our algorithm demonstrates good runtime characteristics for power grids with large numbers of pad candidates in multi-million-size circuits. For a 16-million-node power grid with 646 thousand pad candidates, our algorithm took 72 minutes to improve the worst voltage drop from 0.398V to 0.196V and reduce the deviation of voltages on the power grid from 0.134V to 0.024V.

Original languageEnglish (US)
Title of host publicationProceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Pages763-767
Number of pages5
DOIs
StatePublished - 2007
EventASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan
Duration: Jan 23 2007Jan 27 2007

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

OtherASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
CountryJapan
CityYokohama
Period1/23/071/27/07

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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