Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation

Chung Ping Chen, Yao Wen Chang, D. F. Wong

Research output: Contribution to journalConference articlepeer-review


Delay, power, skew, area, and sensitivity are the most important concerns in current clock-tree design. We present in this paper an algorithm for simultaneously optimizing the above objectives by sizing wires and buffers in clock trees. Our algorithm, based on Lagrangian relaxation method, can optimally minimize delay, power, and area simultaneously with very low skew and sensitivity. With linear storage overall and linear runtime per iteration, our algorithm is extremely economical, fast, and accurate; for example, our algorithm can solve a 6201-wire-segment clock-tree problem using about 1-minute runtime and 1.3-MB memory and still achieve pico-second precision on an IBM RS/6000 workstation.

Original languageEnglish (US)
Pages (from-to)405-408
Number of pages4
JournalProceedings - Design Automation Conference
StatePublished - 1996
Externally publishedYes
EventProceedings of the 1996 33rd Annual Design Automation Conference - Las Vegas, NV, USA
Duration: Jun 3 1996Jun 7 1996

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering


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