TY - GEN
T1 - Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference
AU - Hurkat, Skand
AU - Choi, Jungwook
AU - Nurvitadhi, Eriko
AU - Martinez, Jose F.
AU - Rutenbar, Rob A.
N1 - Publisher Copyright:
© 2015 Imperial College.
PY - 2015/10/7
Y1 - 2015/10/7
N2 - Maximum a posteriori probability (MAP) inference on Markov random fields (MRF) is the basis of many computer vision applications. Sequential tree-reweighted belief propagation (TRW-S) has been shown to provide very good inference quality and strong convergence properties. However, software TRW-S solvers are slow due to the algorithm's high computational requirements. A state-of-the-art FPGA implementation has been developed recently, which delivers substantial speedup over software. In this paper, we improve upon the TRW-S algorithm by using a multi-level hierarchical MRF formulation. We demonstrate the benefits of Hierarchical-TRW-S over TRW-S, and incorporate the proposed improvements on a Convey HC-1 CPU-FPGA hybrid platform. Results using four Middlebury stereo vision benchmarks show a 21% to 53% reduction in inference time compared with the state-of-the-art TRW-S FPGA implementation. To the best of our knowledge, this is the fastest hardware implementation of TRW-S reported so far.
AB - Maximum a posteriori probability (MAP) inference on Markov random fields (MRF) is the basis of many computer vision applications. Sequential tree-reweighted belief propagation (TRW-S) has been shown to provide very good inference quality and strong convergence properties. However, software TRW-S solvers are slow due to the algorithm's high computational requirements. A state-of-the-art FPGA implementation has been developed recently, which delivers substantial speedup over software. In this paper, we improve upon the TRW-S algorithm by using a multi-level hierarchical MRF formulation. We demonstrate the benefits of Hierarchical-TRW-S over TRW-S, and incorporate the proposed improvements on a Convey HC-1 CPU-FPGA hybrid platform. Results using four Middlebury stereo vision benchmarks show a 21% to 53% reduction in inference time compared with the state-of-the-art TRW-S FPGA implementation. To the best of our knowledge, this is the fastest hardware implementation of TRW-S reported so far.
UR - http://www.scopus.com/inward/record.url?scp=84962343749&partnerID=8YFLogxK
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U2 - 10.1109/FPL.2015.7293934
DO - 10.1109/FPL.2015.7293934
M3 - Conference contribution
AN - SCOPUS:84962343749
T3 - 25th International Conference on Field Programmable Logic and Applications, FPL 2015
BT - 25th International Conference on Field Programmable Logic and Applications, FPL 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 25th International Conference on Field Programmable Logic and Applications, FPL 2015
Y2 - 2 September 2015 through 4 September 2015
ER -