Fast eye diagram analysis for high-speed CMOS circuits

Seyed Nematollah Ahmadyan, Chenjie Gu, Suriyaprakash Natarajan, Eli Chiprout, Shobha Vasudevan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present an efficient technique for analyzing eye diagrams of high speed CMOS circuits in the presence of non-idealities like noise and jitter. Our method involves geometric manipulations of the eye diagram topology to find area within the eye contours. We introduce random tree based simulations as an approach to computing the desired area. We typically show 20× speedup in generating the eye diagram as compared to the state-of-the-art Monte Carlo simulation based eye diagram analysis. For the same number of samples, Monte Carlo produces an eye diagram that is 8.51% smaller than the ideal eye diagram. We generate an eye diagram that is 53.52% smaller than the ideal eye, showing a 47% improvement in quality.

Original languageEnglish (US)
Title of host publicationProceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1377-1382
Number of pages6
Volume2015-April
ISBN (Electronic)9783981537048
StatePublished - Apr 22 2015
Externally publishedYes
Event2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 - Grenoble, France
Duration: Mar 9 2015Mar 13 2015

Other

Other2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
CountryFrance
CityGrenoble
Period3/9/153/13/15

Fingerprint

Jitter
Topology
Networks (circuits)
Monte Carlo simulation

Keywords

  • Eye diagram analysis
  • Nonlinear analog circuits
  • Random tree optimization
  • Signal Integrity

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Ahmadyan, S. N., Gu, C., Natarajan, S., Chiprout, E., & Vasudevan, S. (2015). Fast eye diagram analysis for high-speed CMOS circuits. In Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 (Vol. 2015-April, pp. 1377-1382). [7092606] Institute of Electrical and Electronics Engineers Inc..

Fast eye diagram analysis for high-speed CMOS circuits. / Ahmadyan, Seyed Nematollah; Gu, Chenjie; Natarajan, Suriyaprakash; Chiprout, Eli; Vasudevan, Shobha.

Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Vol. 2015-April Institute of Electrical and Electronics Engineers Inc., 2015. p. 1377-1382 7092606.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ahmadyan, SN, Gu, C, Natarajan, S, Chiprout, E & Vasudevan, S 2015, Fast eye diagram analysis for high-speed CMOS circuits. in Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. vol. 2015-April, 7092606, Institute of Electrical and Electronics Engineers Inc., pp. 1377-1382, 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015, Grenoble, France, 3/9/15.
Ahmadyan SN, Gu C, Natarajan S, Chiprout E, Vasudevan S. Fast eye diagram analysis for high-speed CMOS circuits. In Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Vol. 2015-April. Institute of Electrical and Electronics Engineers Inc. 2015. p. 1377-1382. 7092606
Ahmadyan, Seyed Nematollah ; Gu, Chenjie ; Natarajan, Suriyaprakash ; Chiprout, Eli ; Vasudevan, Shobha. / Fast eye diagram analysis for high-speed CMOS circuits. Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Vol. 2015-April Institute of Electrical and Electronics Engineers Inc., 2015. pp. 1377-1382
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