Fast circuit simulator for transient analysis of CDM ESD

Kuo Hsuan Meng, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The run-time for circuit-level CDM ESD simulation can be prohibitively long. By leveraging the specific properties of the problem formulation, run-time can be reduced without compromising accuracy. A reduced run-time is obtained by using cluster computing, and additional speed-up is achieved using specialized device models and a customized simulation engine.

Original languageEnglish (US)
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS/ESD 2015
PublisherESD Association
ISBN (Electronic)1585372722, 9781585372737
StatePublished - Oct 30 2015
Event37th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2015 - Reno, United States
Duration: Sep 27 2015Oct 2 2015

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
Volume2015-October
ISSN (Print)0739-5159

Other

Other37th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2015
Country/TerritoryUnited States
CityReno
Period9/27/1510/2/15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Fast circuit simulator for transient analysis of CDM ESD'. Together they form a unique fingerprint.

Cite this