Fast Boolean matching for field-programmable gate arrays

Kai Zhu, D. F. Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A key step in technology mapping for non lookup-table (such as multiplexor) based FPGAs is to determine whether a given function can be implemented by the logic module. A new algorithm is presented for solving this problem. The algorithm is based on a character string representation of binary decision diagrams. Such representation leads to a matching algorithm which requires only a few string comparisons for each matching operation. Comparing to the matching algorithm by searching for isomorphism on all different BDDs, the new algorithm is much faster with a modest increase of memory requirement.

Original languageEnglish (US)
Title of host publicationEuropean Design Automation Conference - Proceedings
Editors Anon
PublisherPubl by IEEE
Pages352-357
Number of pages6
ISBN (Print)0818643528
StatePublished - Dec 1 1993
Externally publishedYes

Publication series

NameEuropean Design Automation Conference - Proceedings

ASJC Scopus subject areas

  • Control and Systems Engineering

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  • Cite this

    Zhu, K., & Wong, D. F. (1993). Fast Boolean matching for field-programmable gate arrays. In Anon (Ed.), European Design Automation Conference - Proceedings (pp. 352-357). (European Design Automation Conference - Proceedings). Publ by IEEE.